72 lines
3.6 KiB
C
72 lines
3.6 KiB
C
/**************************************************************************************
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* Copyright (c) 2016-2017, ARM Limited or its affiliates. All rights reserved *
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* *
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* This file and the related binary are licensed under the following license: *
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* *
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* ARM Object Code and Header Files License, v1.0 Redistribution. *
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* *
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* Redistribution and use of object code, header files, and documentation, without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1) Redistributions must reproduce the above copyright notice and the *
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* following disclaimer in the documentation and/or other materials *
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* provided with the distribution. *
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* *
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* 2) Unless to the extent explicitly permitted by law, no reverse *
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* engineering, decompilation, or disassembly of is permitted. *
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* *
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* 3) Redistribution and use is permitted solely for the purpose of *
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* developing or executing applications that are targeted for use *
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* on an ARM-based product. *
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* *
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* DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
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* CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT *
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* NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, *
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE *
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED *
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR *
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING *
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS *
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
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**************************************************************************************/
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#ifndef _SSI_PAL_BARRIER_H
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#define _SSI_PAL_BARRIER_H
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/*!
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@file
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@brief This file contains the definitions and APIs for memory barrier implementation.
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This is a place holder for platform specific memory barrier implementation
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The secure core driver should include a memory barrier before and after the last word of the descriptor
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to allow correct order between the words and different descriptors.
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@defgroup ssi_pal_barrier CryptoCell PAL memory Barrier APIs
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@{
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@ingroup ssi_pal
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*/
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/*!
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* This MACRO is responsible to put the memory barrier after the write operation.
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*
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* @return None
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*/
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void SaSi_PalWmb(void);
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/*!
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* This MACRO is responsible to put the memory barrier before the read operation.
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*
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* @return None
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*/
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void SaSi_PalRmb(void);
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/**
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@}
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*/
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#endif
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