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modules/nrfx/soc/nrfx_atomic.c Normal file
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/**
* Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "nrfx_atomic.h"
#ifndef NRFX_ATOMIC_USE_BUILT_IN
#define NRFX_ATOMIC_USE_BUILT_IN 0
#endif // NRFX_ATOMIC_USE_BUILT_IN
#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U))
#define NRFX_ATOMIC_STREX_LDREX_PRESENT
#endif
#if (NRFX_ATOMIC_USE_BUILT_IN == 0) && defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
#include "nrfx_atomic_internal.h"
#endif
uint32_t nrfx_atomic_u32_fetch_store(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_exchange_n(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(mov, old_val, new_val, p_data, value);
(void) new_val;
return old_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
uint32_t old_val = *p_data;
*p_data = value;
NRFX_CRITICAL_SECTION_EXIT();
return old_val;
#endif // NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_store(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
__atomic_store_n(p_data, value, __ATOMIC_SEQ_CST);
return value;
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(mov, old_val, new_val, p_data, value);
(void) old_val;
return new_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
*p_data = value;
NRFX_CRITICAL_SECTION_EXIT();
return value;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_fetch_or(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_fetch_or(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(orr, old_val, new_val, p_data, value);
(void) new_val;
return old_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
uint32_t old_val = *p_data;
*p_data |= value;
NRFX_CRITICAL_SECTION_EXIT();
return old_val;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_or(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_or_fetch(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(orr, old_val, new_val, p_data, value);
(void) old_val;
return new_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
*p_data |= value;
uint32_t new_value = *p_data;
NRFX_CRITICAL_SECTION_EXIT();
return new_value;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_fetch_and(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_fetch_and(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(and, old_val, new_val, p_data, value);
(void) new_val;
return old_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
uint32_t old_val = *p_data;
*p_data &= value;
NRFX_CRITICAL_SECTION_EXIT();
return old_val;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_and(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_and_fetch(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(and, old_val, new_val, p_data, value);
(void) old_val;
return new_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
*p_data &= value;
uint32_t new_value = *p_data;
NRFX_CRITICAL_SECTION_EXIT();
return new_value;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_fetch_xor(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_fetch_xor(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(eor, old_val, new_val, p_data, value);
(void) new_val;
return old_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
uint32_t old_val = *p_data;
*p_data ^= value;
NRFX_CRITICAL_SECTION_EXIT();
return old_val;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_xor(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_xor_fetch(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(eor, old_val, new_val, p_data, value);
(void) old_val;
return new_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
*p_data ^= value;
uint32_t new_value = *p_data;
NRFX_CRITICAL_SECTION_EXIT();
return new_value;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_fetch_add(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_fetch_add(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(add, old_val, new_val, p_data, value);
(void) new_val;
return old_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
uint32_t old_val = *p_data;
*p_data += value;
NRFX_CRITICAL_SECTION_EXIT();
return old_val;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_add(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_add_fetch(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(add, old_val, new_val, p_data, value);
(void) old_val;
return new_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
*p_data += value;
uint32_t new_value = *p_data;
NRFX_CRITICAL_SECTION_EXIT();
return new_value;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_fetch_sub(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_fetch_sub(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(sub, old_val, new_val, p_data, value);
(void) new_val;
return old_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
uint32_t old_val = *p_data;
*p_data -= value;
NRFX_CRITICAL_SECTION_EXIT();
return old_val;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_sub(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_sub_fetch(p_data, value, __ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(sub, old_val, new_val, p_data, value);
(void) old_val;
return new_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
*p_data -= value;
uint32_t new_value = *p_data;
NRFX_CRITICAL_SECTION_EXIT();
return new_value;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
bool nrfx_atomic_u32_cmp_exch(nrfx_atomic_u32_t * p_data,
uint32_t * p_expected,
uint32_t desired)
{
#if NRFX_ATOMIC_USE_BUILT_IN
return __atomic_compare_exchange(p_data,
p_expected,
&desired,
1,
__ATOMIC_SEQ_CST,
__ATOMIC_SEQ_CST);
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
return nrfx_atomic_internal_cmp_exch(p_data, p_expected, desired);
#else
bool result;
NRFX_CRITICAL_SECTION_ENTER();
if (*p_data == *p_expected)
{
*p_data = desired;
result = true;
}
else
{
*p_expected = *p_data;
result = false;
}
NRFX_CRITICAL_SECTION_EXIT();
return result;
#endif
}
uint32_t nrfx_atomic_u32_fetch_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
uint32_t expected = *p_data;
uint32_t new_val;
do {
if (expected >= value)
{
new_val = expected - value;
}
else
{
new_val = expected;
}
} while (!__atomic_compare_exchange(p_data, &expected, &new_val,
1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST));
return expected;
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(sub_hs, old_val, new_val, p_data, value);
(void) new_val;
return old_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
uint32_t old_val = *p_data;
*p_data -= value;
NRFX_CRITICAL_SECTION_EXIT();
return old_val;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_u32_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value)
{
#if NRFX_ATOMIC_USE_BUILT_IN
uint32_t expected = *p_data;
uint32_t new_val;
do {
if (expected >= value)
{
new_val = expected - value;
}
else
{
new_val = expected;
}
} while (!__atomic_compare_exchange(p_data, &expected, &new_val,
1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST));
return new_val;
#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT)
uint32_t old_val;
uint32_t new_val;
NRFX_ATOMIC_OP(sub_hs, old_val, new_val, p_data, value);
(void) old_val;
return new_val;
#else
NRFX_CRITICAL_SECTION_ENTER();
*p_data -= value;
uint32_t new_value = *p_data;
NRFX_CRITICAL_SECTION_EXIT();
return new_value;
#endif //NRFX_ATOMIC_USE_BUILT_IN
}
uint32_t nrfx_atomic_flag_set_fetch(nrfx_atomic_flag_t * p_data)
{
return nrfx_atomic_u32_fetch_or(p_data, 1);
}
uint32_t nrfx_atomic_flag_set(nrfx_atomic_flag_t * p_data)
{
return nrfx_atomic_u32_or(p_data, 1);
}
uint32_t nrfx_atomic_flag_clear_fetch(nrfx_atomic_flag_t * p_data)
{
return nrfx_atomic_u32_fetch_and(p_data, 0);
}
uint32_t nrfx_atomic_flag_clear(nrfx_atomic_flag_t * p_data)
{
return nrfx_atomic_u32_and(p_data, 0);
}

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modules/nrfx/soc/nrfx_atomic.h Normal file
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/**
* Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_ATOMIC_H__
#define NRFX_ATOMIC_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrfx_atomic Atomic operations API
* @ingroup nrfx
* @{
*
* @brief This module implements C11 stdatomic.h simplified API.
*
* At this point, only Cortex-M3 and M4 cores are supported (LDREX/STREX instructions).
* Atomic types are limited to @ref nrfx_atomic_u32_t and @ref nrfx_atomic_flag_t.
*/
/** @brief Atomic 32-bit unsigned type. */
typedef volatile uint32_t nrfx_atomic_u32_t;
/** @brief Atomic 1-bit flag type (technically 32-bit). */
typedef volatile uint32_t nrfx_atomic_flag_t;
/**
* @brief Function for storing a value to an atomic object and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value to store.
*
* @return Previous value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_store(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for storing a value to an atomic object and returning its new value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value to store.
*
* @return New value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_store(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running a logical OR operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the OR operation.
*
* @return Previous value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_or(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running a logical OR operation on an atomic object
* and returning its new value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the OR operation.
*
* @return New value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_or(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running a logical AND operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the AND operation.
*
* @return Previous value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_and(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running a logical AND operation on an atomic object
* and returning its new value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the AND operation.
*
* @return New value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_and(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running a logical XOR operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the XOR operation.
*
* @return Previous value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_xor(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running a logical XOR operation on an atomic object
* and returning its new value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the XOR operation.
*
* @return New value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_xor(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running an arithmetic ADD operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the ADD operation.
*
* @return Previous value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_add(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running an arithmetic ADD operation on an atomic object
* and returning its new value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the ADD operation.
*
* @return New value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_add(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running an arithmetic SUB operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the SUB operation.
*
* @return Old value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_sub(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running an arithmetic SUB operation on an atomic object
* and returning its new value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the SUB operation.
*
* @return New value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_sub(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for atomic conditional value replacement.
*
* Atomically compares the value pointed to by @p p_data with the value pointed to by @p p_expected.
* If those are equal, replaces the former with desired. Otherwise, loads the actual value
* pointed to by @p p_data into @p *p_expected.
*
* @param p_data Atomic memory pointer to test and modify.
* @param p_expected Pointer to the test value.
* @param desired Value to be stored to atomic memory.
*
* @retval true @p *p_data was equal to @p *p_expected.
* @retval false @p *p_data was not equal to @p *p_expected.
*/
bool nrfx_atomic_u32_cmp_exch(nrfx_atomic_u32_t * p_data,
uint32_t * p_expected,
uint32_t desired);
/**
* @brief Function for running an arithmetic SUB operation on an atomic object
* if object >= value, and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the SUB operation.
*
* @return Previous value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running an arithmetic SUB operation on an atomic object
* if object >= value, and returning its new value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the SUB operation.
*
* @return New value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
* @brief Function for running a logical one bit flag set operation
* on an atomic object and returning its previous value.
*
* @param[in] p_data Atomic flag memory pointer.
*
* @return Previous flag value.
*/
uint32_t nrfx_atomic_flag_set_fetch(nrfx_atomic_flag_t * p_data);
/**
* @brief Function for running a logical one bit flag set operation
* on an atomic object and returning its new value.
*
* @param[in] p_data Atomic flag memory pointer.
*
* @return New flag value.
*/
uint32_t nrfx_atomic_flag_set(nrfx_atomic_flag_t * p_data);
/**
* @brief Function for running a logical one bit flag clear operation
* on an atomic object and returning its previous value.
*
* @param[in] p_data Atomic flag memory pointer.
*
* @return Previous flag value.
*/
uint32_t nrfx_atomic_flag_clear_fetch(nrfx_atomic_flag_t * p_data);
/**
* @brief Function for running a logical one bit flag clear operation
* on an atomic object and returning its new value.
*
* @param[in] p_data Atomic flag memory pointer.
*
* @return New flag value.
*/
uint32_t nrfx_atomic_flag_clear(nrfx_atomic_flag_t * p_data);
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRFX_ATOMIC_H__

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/**
* Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_ATOMIC_INTERNAL_H__
#define NRFX_ATOMIC_INTERNAL_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Only Cortex-M cores > 3 support LDREX/STREX instructions. */
#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) == 0
#error "Unsupported core version"
#endif
#if defined ( __CC_ARM )
static __asm uint32_t nrfx_atomic_internal_mov(nrfx_atomic_u32_t * p_ptr,
uint32_t value,
uint32_t * p_new)
{
/* The base standard specifies that arguments are passed in the core registers
* r0-r3 and on the stack. Registers r4 and r5 must be saved on the stack.
* Only even number of register pushes are allowed. This is a requirement
* of the Procedure Call Standard for the ARM Architecture [AAPCS].
*/
push {r4, r5}
mov r4, r0
loop_mov
ldrex r0, [r4]
mov r5, r1
strex r3, r5, [r4]
cmp r3, #0
bne loop_mov
str r5, [r2]
pop {r4, r5}
bx lr
}
static __asm uint32_t nrfx_atomic_internal_orr(nrfx_atomic_u32_t * p_ptr,
uint32_t value,
uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
loop_orr
ldrex r0, [r4]
orr r5, r0, r1
strex r3, r5, [r4]
cmp r3, #0
bne loop_orr
str r5, [r2]
pop {r4, r5}
bx lr
}
static __asm uint32_t nrfx_atomic_internal_and(nrfx_atomic_u32_t * p_ptr,
uint32_t value,
uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
loop_and
ldrex r0, [r4]
and r5, r0, r1
strex r3, r5, [r4]
cmp r3, #0
bne loop_and
str r5, [r2]
pop {r4, r5}
bx lr
}
static __asm uint32_t nrfx_atomic_internal_eor(nrfx_atomic_u32_t * p_ptr,
uint32_t value,
uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
loop_eor
ldrex r0, [r4]
eor r5, r0, r1
strex r3, r5, [r4]
cmp r3, #0
bne loop_eor
str r5, [r2]
pop {r4, r5}
bx lr
}
static __asm uint32_t nrfx_atomic_internal_add(nrfx_atomic_u32_t * p_ptr,
uint32_t value,
uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
loop_add
ldrex r0, [r4]
add r5, r0, r1
strex r3, r5, [r4]
cmp r3, #0
bne loop_add
str r5, [r2]
pop {r4, r5}
bx lr
}
static __asm uint32_t nrfx_atomic_internal_sub(nrfx_atomic_u32_t * p_ptr,
uint32_t value,
uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
loop_sub
ldrex r0, [r4]
sub r5, r0, r1
strex r3, r5, [r4]
cmp r3, #0
bne loop_sub
str r5, [r2]
pop {r4, r5}
bx lr
}
static __asm bool nrfx_atomic_internal_cmp_exch(nrfx_atomic_u32_t * p_data,
uint32_t * p_expected,
uint32_t value)
{
#define RET_REG r0
#define P_EXPC r1
#define VALUE r2
#define STR_RES r3
#define P_DATA r4
#define EXPC_VAL r5
#define ACT_VAL r6
push {r4-r6}
mov P_DATA, r0
mov RET_REG, #0
loop_cmp_exch
ldrex ACT_VAL, [P_DATA]
ldr EXPC_VAL, [P_EXPC]
cmp ACT_VAL, EXPC_VAL
ittee eq
strexeq STR_RES, VALUE, [P_DATA]
moveq RET_REG, #1
strexne STR_RES, ACT_VAL, [P_DATA]
strne ACT_VAL, [P_EXPC]
cmp STR_RES, #0
itt ne
movne RET_REG, #0
bne loop_cmp_exch
pop {r4-r6}
bx lr
#undef RET_REG
#undef P_EXPC
#undef VALUE
#undef STR_RES
#undef P_DATA
#undef EXPC_VAL
#undef ACT_VAL
}
static __asm uint32_t nrfx_atomic_internal_sub_hs(nrfx_atomic_u32_t * p_ptr,
uint32_t value,
uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
loop_sub_ge
ldrex r0, [r4]
cmp r0, r1
ite hs
subhs r5, r0, r1
movlo r5, r0
strex r3, r5, [r4]
cmp r3, #0
bne loop_sub_ge
str r5, [r2]
pop {r4, r5}
bx lr
}
#define NRFX_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \
old_val = nrfx_atomic_internal_##asm_op(ptr, value, &new_val)
#elif defined ( __ICCARM__ ) || defined ( __GNUC__ )
/**
* @brief Atomic operation generic macro.
*
* @param[in] asm_op Operation: mov, orr, and, eor, add, sub.
* @param[out] old_val Atomic object output (uint32_t); value before operation.
* @param[out] new_val Atomic object output (uint32_t); value after operation.
* @param[in] value Atomic operation operand.
*/
#define NRFX_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \
{ \
uint32_t tmp_reg; \
__ASM volatile( \
"1: ldrex %["#old_val"], [%["#ptr"]]\n" \
NRFX_ATOMIC_OP_##asm_op(new_val, old_val, value) \
" strex %[tmp_reg], %["#new_val"], [%["#ptr"]]\n" \
" teq %[tmp_reg], #0\n" \
" bne.n 1b" \
: \
[old_val] "=&r" (old_val), \
[new_val] "=&r" (new_val), \
[tmp_reg] "=&r" (tmp_reg) \
: \
[ptr] "r" (ptr), \
[value] "r" (value) \
: "cc"); \
(void)tmp_reg; \
}
#define NRFX_ATOMIC_OP_mov(new_val, old_val, value) "mov %["#new_val"], %["#value"]\n"
#define NRFX_ATOMIC_OP_orr(new_val, old_val, value) "orr %["#new_val"], %["#old_val"], %["#value"]\n"
#define NRFX_ATOMIC_OP_and(new_val, old_val, value) "and %["#new_val"], %["#old_val"], %["#value"]\n"
#define NRFX_ATOMIC_OP_eor(new_val, old_val, value) "eor %["#new_val"], %["#old_val"], %["#value"]\n"
#define NRFX_ATOMIC_OP_add(new_val, old_val, value) "add %["#new_val"], %["#old_val"], %["#value"]\n"
#define NRFX_ATOMIC_OP_sub(new_val, old_val, value) "sub %["#new_val"], %["#old_val"], %["#value"]\n"
#define NRFX_ATOMIC_OP_sub_hs(new_val, old_val, value) \
"cmp %["#old_val"], %["#value"]\n " \
"ite hs\n" \
"subhs %["#new_val"], %["#old_val"], %["#value"]\n" \
"movlo %["#new_val"], %["#old_val"]\n"
static inline bool nrfx_atomic_internal_cmp_exch(nrfx_atomic_u32_t * p_data,
uint32_t * p_expected,
uint32_t value)
{
bool res = false;
/* Temporary register used in the inline asm code for getting the result
* of the strex* operations (no need to initialize it).
*/
uint32_t tmp_reg;
uint32_t act_val = 0;
uint32_t exp_val = 0;
__ASM volatile(
"1: ldrex %[act_val], [%[ptr]]\n"
" ldr %[exp_val], [%[expc]]\n"
" cmp %[act_val], %[exp_val]\n"
" ittee eq\n"
" strexeq %[tmp_reg], %[value], [%[ptr]]\n"
" moveq %[res], #1\n"
" strexne %[tmp_reg], %[act_val], [%[ptr]]\n"
" strne %[act_val], [%[expc]]\n"
" cmp %[tmp_reg], #0\n"
" itt ne\n"
" movne %[res], #0\n"
" bne.n 1b"
:
[res] "=&r" (res),
[exp_val] "=&r" (exp_val),
[act_val] "=&r" (act_val),
[tmp_reg] "=&r" (tmp_reg)
:
"0" (res),
"1" (exp_val),
"2" (act_val),
[expc] "r" (p_expected),
[ptr] "r" (p_data),
[value] "r" (value)
: "cc");
(void)tmp_reg;
return res;
}
#else
#error "Unsupported compiler"
#endif
#ifdef __cplusplus
}
#endif
#endif // NRFX_ATOMIC_INTERNAL_H__

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/**
* Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_COREDEP_H__
#define NRFX_COREDEP_H__
/**
* @defgroup nrfx_coredep Core-dependent functionality
* @{
* @ingroup nrfx
* @brief Module containing functions with core-dependent implementation, like delay.
*/
#if defined(__NRFX_DOXYGEN__)
/** @brief Core frequency (in MHz). */
#define NRFX_DELAY_CPU_FREQ_MHZ
/** @brief Availability of Data Watchpoint and Trace (DWT) unit in the given SoC. */
#define NRFX_DELAY_DWT_PRESENT
/**
* @brief Number of cycles consumed by one iteration of the internal loop
* in the function @ref nrfx_coredep_delay_us.
*
* This value can be specified externally (for example, when the SoC is emulated).
*/
#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES
#elif defined(NRF51)
#define NRFX_DELAY_CPU_FREQ_MHZ 16
#define NRFX_DELAY_DWT_PRESENT 0
#elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52820_XXAA)
#define NRFX_DELAY_CPU_FREQ_MHZ 64
#define NRFX_DELAY_DWT_PRESENT 0
#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
defined(NRF52833_XXAA) || defined(NRF52840_XXAA) || \
defined(NRF9160_XXAA)
#define NRFX_DELAY_CPU_FREQ_MHZ 64
#define NRFX_DELAY_DWT_PRESENT 1
#else
#error "Unknown device."
#endif
/**
* @brief Function for delaying execution for a number of microseconds.
*
* The value of @p time_us is multiplied by the frequency in MHz. Therefore, the delay is limited to
* maximum uint32_t capacity divided by frequency. For example:
* - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds)
* - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds)
*
* @sa NRFX_COREDEP_DELAY_US_LOOP_CYCLES
*
* @param time_us Number of microseconds to wait.
*/
__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us);
/** @} */
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
#if NRFX_CHECK(NRFX_DELAY_DWT_BASED)
#if !NRFX_DELAY_DWT_PRESENT
#error "DWT unit not present in the SoC that is used."
#endif
__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
if (time_us == 0)
{
return;
}
uint32_t time_cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
// Save the current state of the DEMCR register to be able to restore it before exiting
// this function. Enable the trace and debug blocks (including DWT).
uint32_t core_debug = CoreDebug->DEMCR;
CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
// Save the current state of the CTRL register in the DWT block. Make sure
// that the cycle counter is enabled.
uint32_t dwt_ctrl = DWT->CTRL;
DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
// Store start value of the cycle counter.
uint32_t cyccnt_initial = DWT->CYCCNT;
// Delay required time.
while ((DWT->CYCCNT - cyccnt_initial) < time_cycles)
{}
// Restore preserved registers.
DWT->CTRL = dwt_ctrl;
CoreDebug->DEMCR = core_debug;
}
#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)
__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
if (time_us == 0)
{
return;
}
// Allow overriding the number of cycles per loop iteration, in case it is
// needed to adjust this number externally (for example, when the SoC is
// emulated).
#ifndef NRFX_COREDEP_DELAY_US_LOOP_CYCLES
#if defined(NRF51)
// The loop takes 4 cycles: 1 for SUBS, 3 for BHI.
#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 4
#elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52820_XXAA)
// The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 wait states
// for each instruction.
#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 7
#else
// The loop takes 3 cycles: 1 for SUBS, 2 for BHI.
#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 3
#endif
#endif // NRFX_COREDEP_DELAY_US_LOOP_CYCLES
// Align the machine code, so that it can be cached properly and no extra
// wait states appear.
__ALIGN(16)
static const uint16_t delay_machine_code[] = {
0x3800 + NRFX_COREDEP_DELAY_US_LOOP_CYCLES, // SUBS r0, #loop_cycles
0xd8fd, // BHI .-2
0x4770 // BX LR
};
typedef void (* delay_func_t)(uint32_t);
const delay_func_t delay_cycles =
// Set LSB to 1 to execute the code in the Thumb mode.
(delay_func_t)((((uint32_t)delay_machine_code) | 1));
uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
delay_cycles(cycles);
}
#endif // !NRFX_CHECK(NRFX_DELAY_DWT_BASED_DELAY)
#endif // SUPPRESS_INLINE_IMPLEMENTATION
#endif // NRFX_COREDEP_H__

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/**
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_H__
#define NRFX_IRQS_H__
#if defined(NRF51)
#include <soc/nrfx_irqs_nrf51.h>
#elif defined(NRF52810_XXAA)
#include <soc/nrfx_irqs_nrf52810.h>
#elif defined(NRF52811_XXAA)
#include <soc/nrfx_irqs_nrf52811.h>
#elif defined(NRF52820_XXAA)
#include <soc/nrfx_irqs_nrf52820.h>
#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
#include <soc/nrfx_irqs_nrf52832.h>
#elif defined(NRF52833_XXAA)
#include <soc/nrfx_irqs_nrf52833.h>
#elif defined(NRF52840_XXAA)
#include <soc/nrfx_irqs_nrf52840.h>
#elif defined(NRF9160_XXAA)
#include <soc/nrfx_irqs_nrf9160.h>
#else
#error "Unknown device."
#endif
#endif // NRFX_IRQS_H__

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/**
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_NRF51_H__
#define NRFX_IRQS_NRF51_H__
#ifdef __cplusplus
extern "C" {
#endif
// POWER_CLOCK_IRQn
#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler
// RADIO_IRQn
// UART0_IRQn
#define nrfx_uart_0_irq_handler UART0_IRQHandler
// SPI0_TWI0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
#define nrfx_prs_box_0_irq_handler SPI0_TWI0_IRQHandler
#else
#define nrfx_spi_0_irq_handler SPI0_TWI0_IRQHandler
#define nrfx_twi_0_irq_handler SPI0_TWI0_IRQHandler
#endif
// SPI1_TWI1_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
#define nrfx_prs_box_1_irq_handler SPI1_TWI1_IRQHandler
#else
#define nrfx_spi_1_irq_handler SPI1_TWI1_IRQHandler
#define nrfx_spis_1_irq_handler SPI1_TWI1_IRQHandler
#define nrfx_twi_1_irq_handler SPI1_TWI1_IRQHandler
#endif
// GPIOTE_IRQn
#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
// ADC_IRQn
#define nrfx_adc_irq_handler ADC_IRQHandler
// TIMER0_IRQn
#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
// TIMER1_IRQn
#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
// TIMER2_IRQn
#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
// RTC0_IRQn
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
// ECB_IRQn
// CCM_AAR_IRQn
// WDT_IRQn
#define nrfx_wdt_irq_handler WDT_IRQHandler
// RTC1_IRQn
#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
// QDEC_IRQn
#define nrfx_qdec_irq_handler QDEC_IRQHandler
// LPCOMP_IRQn
#define nrfx_lpcomp_irq_handler LPCOMP_IRQHandler
// SWI0_IRQn
#define nrfx_swi_0_irq_handler SWI0_IRQHandler
// SWI1_IRQn
#define nrfx_swi_1_irq_handler SWI1_IRQHandler
// SWI2_IRQn
#define nrfx_swi_2_irq_handler SWI2_IRQHandler
// SWI3_IRQn
#define nrfx_swi_3_irq_handler SWI3_IRQHandler
// SWI4_IRQn
#define nrfx_swi_4_irq_handler SWI4_IRQHandler
// SWI5_IRQn
#define nrfx_swi_5_irq_handler SWI5_IRQHandler
#ifdef __cplusplus
}
#endif
#endif // NRFX_IRQS_NRF51_H__

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/**
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_NRF52832_H__
#define NRFX_IRQS_NRF52832_H__
#ifdef __cplusplus
extern "C" {
#endif
// POWER_CLOCK_IRQn
#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler
// RADIO_IRQn
// UARTE0_UART0_IRQn
#if NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
#define nrfx_prs_box_2_irq_handler UARTE0_UART0_IRQHandler
#else
#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler
#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler
#endif
// TWIM0_TWIS0_TWI0_IRQn
#if NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
#define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler
#else
#define nrfx_twim_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler
#define nrfx_twis_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler
#define nrfx_twi_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler
#endif
// SPIM0_SPIS0_SPI0_IRQn
#if NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
#define nrfx_prs_box_1_irq_handler SPIM0_SPIS0_SPI0_IRQHandler
#else
#define nrfx_spim_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler
#define nrfx_spis_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler
#define nrfx_spi_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler
#endif
// GPIOTE_IRQn
#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
// SAADC_IRQn
#define nrfx_saadc_irq_handler SAADC_IRQHandler
// TIMER0_IRQn
#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
// TIMER1_IRQn
#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
// TIMER2_IRQn
#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
// RTC0_IRQn
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
// ECB_IRQn
// CCM_AAR_IRQn
// WDT_IRQn
#define nrfx_wdt_irq_handler WDT_IRQHandler
// RTC1_IRQn
#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
// QDEC_IRQn
#define nrfx_qdec_irq_handler QDEC_IRQHandler
// COMP_IRQn
#define nrfx_comp_irq_handler COMP_IRQHandler
// SWI0_EGU0_IRQn
#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler
// SWI1_EGU1_IRQn
#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler
// SWI2_IRQn
#define nrfx_swi_2_irq_handler SWI2_IRQHandler
// SWI3_IRQn
#define nrfx_swi_3_irq_handler SWI3_IRQHandler
// SWI4_IRQn
#define nrfx_swi_4_irq_handler SWI4_IRQHandler
// SWI5_IRQn
#define nrfx_swi_5_irq_handler SWI5_IRQHandler
// PWM0_IRQn
#define nrfx_pwm_0_irq_handler PWM0_IRQHandler
// PDM_IRQn
#define nrfx_pdm_irq_handler PDM_IRQHandler
#ifdef __cplusplus
}
#endif
#endif // NRFX_IRQS_NRF52832_H__

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/**
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_NRF52811_H__
#define NRFX_IRQS_NRF52811_H__
#ifdef __cplusplus
extern "C" {
#endif
// POWER_CLOCK_IRQn
#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler
// RADIO_IRQn
// UARTE0_UART0_IRQn
#if NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
#define nrfx_prs_box_2_irq_handler UARTE0_UART0_IRQHandler
#else
#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler
#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler
#endif
// TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQ
#if NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
#define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
#else
#define nrfx_twim_0_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
#define nrfx_twis_0_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
#define nrfx_twi_0_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
#define nrfx_spim_1_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
#define nrfx_spis_1_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
#define nrfx_spi_1_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
#endif
// SPIM0_SPIS0_IRQn
#if NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
#define nrfx_prs_box_1_irq_handler SPIM0_SPIS0_SPI0_IRQHandler
#else
#define nrfx_spim_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler
#define nrfx_spis_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler
#define nrfx_spi_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler
#endif
// GPIOTE_IRQn
#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
// SAADC_IRQn
#define nrfx_saadc_irq_handler SAADC_IRQHandler
// TIMER0_IRQn
#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
// TIMER1_IRQn
#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
// TIMER2_IRQn
#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
// RTC0_IRQn
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
// ECB_IRQn
// CCM_AAR_IRQn
// WDT_IRQn
#define nrfx_wdt_irq_handler WDT_IRQHandler
// RTC1_IRQn
#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
// QDEC_IRQn
#define nrfx_qdec_irq_handler QDEC_IRQHandler
// COMP_IRQn
#define nrfx_comp_irq_handler COMP_IRQHandler
// SWI0_EGU0_IRQn
#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler
// SWI1_EGU1_IRQn
#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler
// SWI2_IRQn
#define nrfx_swi_2_irq_handler SWI2_IRQHandler
// SWI3_IRQn
#define nrfx_swi_3_irq_handler SWI3_IRQHandler
// SWI4_IRQn
#define nrfx_swi_4_irq_handler SWI4_IRQHandler
// SWI5_IRQn
#define nrfx_swi_5_irq_handler SWI5_IRQHandler
// PWM0_IRQn
#define nrfx_pwm_0_irq_handler PWM0_IRQHandler
// PDM_IRQn
#define nrfx_pdm_irq_handler PDM_IRQHandler
#ifdef __cplusplus
}
#endif
#endif // NRFX_IRQS_NRF52811_H__

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/**
* Copyright (c) 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_NRF52820_H__
#define NRFX_IRQS_NRF52820_H__
#ifdef __cplusplus
extern "C" {
#endif
// POWER_CLOCK_IRQn
#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler
// RADIO_IRQn
// UARTE0_UART0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
#define nrfx_prs_box_2_irq_handler UARTE0_UART0_IRQHandler
#else
#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler
#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler
#endif
// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#else
#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#endif
// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#else
#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#endif
// GPIOTE_IRQn
#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
// TIMER0_IRQn
#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
// TIMER1_IRQn
#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
// TIMER2_IRQn
#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
// RTC0_IRQn
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
// ECB_IRQn
// CCM_AAR_IRQn
// WDT_IRQn
#define nrfx_wdt_irq_handler WDT_IRQHandler
// RTC1_IRQn
#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
// QDEC_IRQn
#define nrfx_qdec_irq_handler QDEC_IRQHandler
// COMP_IRQn
#define nrfx_comp_irq_handler COMP_IRQHandler
// SWI0_EGU0_IRQn
#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler
// SWI1_EGU1_IRQn
#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler
// SWI2_EGU2_IRQn
#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler
// SWI3_EGU3_IRQn
#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler
// SWI4_EGU4_IRQn
#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler
// SWI5_EGU5_IRQn
#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler
// TIMER3_IRQn
#define nrfx_timer_3_irq_handler TIMER3_IRQHandler
// USBD_IRQn
#define nrfx_usbd_irq_handler USBD_IRQHandler
#ifdef __cplusplus
}
#endif
#endif // NRFX_IRQS_NRF52820_H__

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/**
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_NRF52832_H__
#define NRFX_IRQS_NRF52832_H__
#ifdef __cplusplus
extern "C" {
#endif
// POWER_CLOCK_IRQn
#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler
// RADIO_IRQn
// UARTE0_UART0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED)
#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler
#else
#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler
#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler
#endif
// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#else
#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#endif
// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#else
#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#endif
// NFCT_IRQn
#define nrfx_nfct_irq_handler NFCT_IRQHandler
// GPIOTE_IRQn
#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
// SAADC_IRQn
#define nrfx_saadc_irq_handler SAADC_IRQHandler
// TIMER0_IRQn
#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
// TIMER1_IRQn
#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
// TIMER2_IRQn
#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
// RTC0_IRQn
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
// ECB_IRQn
// CCM_AAR_IRQn
// WDT_IRQn
#define nrfx_wdt_irq_handler WDT_IRQHandler
// RTC1_IRQn
#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
// QDEC_IRQn
#define nrfx_qdec_irq_handler QDEC_IRQHandler
// COMP_LPCOMP_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED)
#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler
#else
#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler
#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler
#endif
// SWI0_EGU0_IRQn
#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler
// SWI1_EGU1_IRQn
#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler
// SWI2_EGU2_IRQn
#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler
// SWI3_EGU3_IRQn
#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler
// SWI4_EGU4_IRQn
#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler
// SWI5_EGU5_IRQn
#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler
// TIMER3_IRQn
#define nrfx_timer_3_irq_handler TIMER3_IRQHandler
// TIMER4_IRQn
#define nrfx_timer_4_irq_handler TIMER4_IRQHandler
// PWM0_IRQn
#define nrfx_pwm_0_irq_handler PWM0_IRQHandler
// PDM_IRQn
#define nrfx_pdm_irq_handler PDM_IRQHandler
// MWU_IRQn
// PWM1_IRQn
#define nrfx_pwm_1_irq_handler PWM1_IRQHandler
// PWM2_IRQn
#define nrfx_pwm_2_irq_handler PWM2_IRQHandler
// SPIM2_SPIS2_SPI2_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#else
#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#endif
// RTC2_IRQn
#define nrfx_rtc_2_irq_handler RTC2_IRQHandler
// I2S_IRQn
#define nrfx_i2s_irq_handler I2S_IRQHandler
// FPU_IRQn
#ifdef __cplusplus
}
#endif
#endif // NRFX_IRQS_NRF52832_H__

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/**
* Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_NRF52833_H__
#define NRFX_IRQS_NRF52833_H__
#ifdef __cplusplus
extern "C" {
#endif
// POWER_CLOCK_IRQn
#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler
// RADIO_IRQn
// UARTE0_UART0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED)
#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler
#else
#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler
#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler
#endif
// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#else
#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#endif
// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#else
#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#endif
// NFCT_IRQn
#define nrfx_nfct_irq_handler NFCT_IRQHandler
// GPIOTE_IRQn
#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
// SAADC_IRQn
#define nrfx_saadc_irq_handler SAADC_IRQHandler
// TIMER0_IRQn
#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
// TIMER1_IRQn
#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
// TIMER2_IRQn
#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
// RTC0_IRQn
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
// ECB_IRQn
// CCM_AAR_IRQn
// WDT_IRQn
#define nrfx_wdt_irq_handler WDT_IRQHandler
// RTC1_IRQn
#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
// QDEC_IRQn
#define nrfx_qdec_irq_handler QDEC_IRQHandler
// COMP_LPCOMP_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED)
#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler
#else
#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler
#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler
#endif
// SWI0_EGU0_IRQn
#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler
// SWI1_EGU1_IRQn
#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler
// SWI2_EGU2_IRQn
#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler
// SWI3_EGU3_IRQn
#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler
// SWI4_EGU4_IRQn
#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler
// SWI5_EGU5_IRQn
#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler
// TIMER3_IRQn
#define nrfx_timer_3_irq_handler TIMER3_IRQHandler
// TIMER4_IRQn
#define nrfx_timer_4_irq_handler TIMER4_IRQHandler
// PWM0_IRQn
#define nrfx_pwm_0_irq_handler PWM0_IRQHandler
// PDM_IRQn
#define nrfx_pdm_irq_handler PDM_IRQHandler
// MWU_IRQn
// PWM1_IRQn
#define nrfx_pwm_1_irq_handler PWM1_IRQHandler
// PWM2_IRQn
#define nrfx_pwm_2_irq_handler PWM2_IRQHandler
// SPIM2_SPIS2_SPI2_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#else
#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#endif
// RTC2_IRQn
#define nrfx_rtc_2_irq_handler RTC2_IRQHandler
// I2S_IRQn
#define nrfx_i2s_irq_handler I2S_IRQHandler
// FPU_IRQn
// USBD_IRQn
#define nrfx_usbd_irq_handler USBD_IRQHandler
// UARTE1_IRQn
#define nrfx_uarte_1_irq_handler UARTE1_IRQHandler
// PWM3_IRQn
#define nrfx_pwm_3_irq_handler PWM3_IRQHandler
// SPIM3_IRQn
#define nrfx_spim_3_irq_handler SPIM3_IRQHandler
#ifdef __cplusplus
}
#endif
#endif // NRFX_IRQS_NRF52833_H__

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/**
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_NRF52840_H__
#define NRFX_IRQS_NRF52840_H__
#ifdef __cplusplus
extern "C" {
#endif
// POWER_CLOCK_IRQn
#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler
// RADIO_IRQn
// UARTE0_UART0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED)
#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler
#else
#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler
#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler
#endif
// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#else
#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
#endif
// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#else
#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
#endif
// NFCT_IRQn
#define nrfx_nfct_irq_handler NFCT_IRQHandler
// GPIOTE_IRQn
#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
// SAADC_IRQn
#define nrfx_saadc_irq_handler SAADC_IRQHandler
// TIMER0_IRQn
#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
// TIMER1_IRQn
#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
// TIMER2_IRQn
#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
// RTC0_IRQn
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
// ECB_IRQn
// CCM_AAR_IRQn
// WDT_IRQn
#define nrfx_wdt_irq_handler WDT_IRQHandler
// RTC1_IRQn
#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
// QDEC_IRQn
#define nrfx_qdec_irq_handler QDEC_IRQHandler
// COMP_LPCOMP_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED)
#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler
#else
#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler
#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler
#endif
// SWI0_EGU0_IRQn
#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler
// SWI1_EGU1_IRQn
#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler
// SWI2_EGU2_IRQn
#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler
// SWI3_EGU3_IRQn
#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler
// SWI4_EGU4_IRQn
#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler
// SWI5_EGU5_IRQn
#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler
// TIMER3_IRQn
#define nrfx_timer_3_irq_handler TIMER3_IRQHandler
// TIMER4_IRQn
#define nrfx_timer_4_irq_handler TIMER4_IRQHandler
// PWM0_IRQn
#define nrfx_pwm_0_irq_handler PWM0_IRQHandler
// PDM_IRQn
#define nrfx_pdm_irq_handler PDM_IRQHandler
// MWU_IRQn
// PWM1_IRQn
#define nrfx_pwm_1_irq_handler PWM1_IRQHandler
// PWM2_IRQn
#define nrfx_pwm_2_irq_handler PWM2_IRQHandler
// SPIM2_SPIS2_SPI2_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#else
#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
#endif
// RTC2_IRQn
#define nrfx_rtc_2_irq_handler RTC2_IRQHandler
// I2S_IRQn
#define nrfx_i2s_irq_handler I2S_IRQHandler
// FPU_IRQn
// USBD_IRQn
#define nrfx_usbd_irq_handler USBD_IRQHandler
// UARTE1_IRQn
#define nrfx_uarte_1_irq_handler UARTE1_IRQHandler
// QSPI_IRQn
#define nrfx_qspi_irq_handler QSPI_IRQHandler
// CRYPTOCELL_IRQn
// PWM3_IRQn
#define nrfx_pwm_3_irq_handler PWM3_IRQHandler
// SPIM3_IRQn
#define nrfx_spim_3_irq_handler SPIM3_IRQHandler
#ifdef __cplusplus
}
#endif
#endif // NRFX_IRQS_NRF52840_H__

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/**
* Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_IRQS_NRF9160_H__
#define NRFX_IRQS_NRF9160_H__
#ifdef __cplusplus
extern "C" {
#endif
// SPU_IRQn
// CLOCK_POWER_IRQn
#define nrfx_power_clock_irq_handler CLOCK_POWER_IRQHandler
// UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
#define nrfx_prs_box_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
#else
#define nrfx_spim_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
#define nrfx_spis_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
#define nrfx_twim_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
#define nrfx_twis_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
#define nrfx_uarte_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
#endif
// UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
#define nrfx_prs_box_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
#else
#define nrfx_spim_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
#define nrfx_spis_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
#define nrfx_twim_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
#define nrfx_twis_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
#define nrfx_uarte_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
#endif
// UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
#define nrfx_prs_box_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
#else
#define nrfx_spim_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
#define nrfx_spis_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
#define nrfx_twim_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
#define nrfx_twis_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
#define nrfx_uarte_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
#endif
// UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED)
#define nrfx_prs_box_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
#else
#define nrfx_spim_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
#define nrfx_spis_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
#define nrfx_twim_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
#define nrfx_twis_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
#define nrfx_uarte_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
#endif
// GPIOTE0_IRQn
#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
// SAADC_IRQn
#define nrfx_saadc_irq_handler SAADC_IRQHandler
// TIMER0_IRQn
#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
// TIMER1_IRQn
#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
// TIMER2_IRQn
#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
// RTC0_IRQn
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// RTC1_IRQn
#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
// WDT_IRQn
#define nrfx_wdt_irq_handler WDT_IRQHandler
// EGU0_IRQn
#define nrfx_swi_0_irq_handler EGU0_IRQHandler
// EGU1_IRQn
#define nrfx_swi_1_irq_handler EGU1_IRQHandler
// EGU2_IRQn
#define nrfx_swi_2_irq_handler EGU2_IRQHandler
// EGU3_IRQn
#define nrfx_swi_3_irq_handler EGU3_IRQHandler
// EGU4_IRQn
#define nrfx_swi_4_irq_handler EGU4_IRQHandler
// EGU5_IRQn
#define nrfx_swi_5_irq_handler EGU5_IRQHandler
// PWM0_IRQn
#define nrfx_pwm_0_irq_handler PWM0_IRQHandler
// PWM1_IRQn
#define nrfx_pwm_1_irq_handler PWM1_IRQHandler
// PWM2_IRQn
#define nrfx_pwm_2_irq_handler PWM2_IRQHandler
// PWM3_IRQn
#define nrfx_pwm_3_irq_handler PWM3_IRQHandler
// PDM_IRQn
#define nrfx_pdm_irq_handler PDM_IRQHandler
// I2S_IRQn
#define nrfx_i2s_irq_handler I2S_IRQHandler
// FPU_IRQn
// GPIOTE1_IRQn
// KMU_IRQn
// CRYPTOCELL_IRQn
#ifdef __cplusplus
}
#endif
#endif // NRFX_IRQS_NRF9160_H__