246 lines
10 KiB
C
246 lines
10 KiB
C
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/*
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Copyright (c) 2009-2020 ARM Limited. All rights reserved.
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SPDX-License-Identifier: Apache-2.0
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Licensed under the Apache License, Version 2.0 (the License); you may
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not use this file except in compliance with the License.
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You may obtain a copy of the License at
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www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an AS IS BASIS, WITHOUT
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WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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NOTICE: This file has been modified by Nordic Semiconductor ASA.
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*/
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/* NOTE: Template files (including this one) are application specific and therefore expected to
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be copied into the application project folder prior to its use! */
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#include <stdint.h>
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#include <stdbool.h>
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#include "nrf.h"
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#include "nrf_erratas.h"
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#include "system_nrf5340_application.h"
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/*lint ++flb "Enter library region" */
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/* NRF5340 application core uses a variable System Clock Frequency that starts at 64MHz */
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#define __SYSTEM_CLOCK_MAX (128000000UL)
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#define __SYSTEM_CLOCK_INITIAL ( 64000000UL)
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#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \
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(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \
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(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \
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(GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \
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(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | \
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(GPIO_PIN_CNF_MCUSEL_TND << GPIO_PIN_CNF_MCUSEL_Pos))
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#define TRACE_TRACECLK_PIN TAD_PSEL_TRACECLK_PIN_Traceclk
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#define TRACE_TRACEDATA0_PIN TAD_PSEL_TRACEDATA0_PIN_Tracedata0
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#define TRACE_TRACEDATA1_PIN TAD_PSEL_TRACEDATA1_PIN_Tracedata1
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#define TRACE_TRACEDATA2_PIN TAD_PSEL_TRACEDATA2_PIN_Tracedata2
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#define TRACE_TRACEDATA3_PIN TAD_PSEL_TRACEDATA3_PIN_Tracedata3
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#if defined ( __CC_ARM )
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uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_INITIAL;
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#elif defined ( __ICCARM__ )
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__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_INITIAL;
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#elif defined ( __GNUC__ )
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uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_INITIAL;
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#endif
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void SystemCoreClockUpdate(void)
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{
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#if defined(NRF_TRUSTZONE_NONSECURE)
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SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_NS->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
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#else
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SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_S->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
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#endif
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}
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void SystemInit(void)
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{
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#if !defined(NRF_TRUSTZONE_NONSECURE)
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/* Perform Secure-mode initialization routines. */
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/* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
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* Nordic SPU should handle Secure Attribution tasks */
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
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#endif
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/* Workaround for Errata 97 "ERASEPROTECT, APPROTECT, or startup problems" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/index.jsp */
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if (nrf53_errata_97())
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{
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if (*((volatile uint32_t *)0x50004A20ul) == 0)
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{
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*((volatile uint32_t *)0x50004A20ul) = 0xDul;
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*((volatile uint32_t *)0x5000491Cul) = 0x1ul;
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*((volatile uint32_t *)0x5000491Cul) = 0x0ul;
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}
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}
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/* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
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until one ADDR is not initialized. */
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uint32_t index = 0;
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for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
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#if defined ( __ICCARM__ )
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/* IAR will complain about the order of volatile pointer accesses. */
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#pragma diag_suppress=Pa082
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#endif
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*NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
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#if defined ( __ICCARM__ )
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#pragma diag_default=Pa082
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#endif
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}
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/* errata 64 must be before errata 42, as errata 42 is dependant on the changes in errata 64*/
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/* Workaround for Errata 64 "VREGMAIN has invalid configuration when CPU is running at 128 MHz" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/index.jsp */
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if (nrf53_errata_64())
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{
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*((volatile uint32_t *)0x5000470Cul) = 0x29ul;
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*((volatile uint32_t *)0x5000473Cul) = 0x3ul;
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}
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/* Workaround for Errata 42 "Reset value of HFCLKCTRL is invalid" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/index.jsp */
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if (nrf53_errata_42())
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{
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*((volatile uint32_t *)0x50039530ul) = 0xBEEF0044ul;
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NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div2 << CLOCK_HFCLKCTRL_HCLK_Pos;
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}
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/* Workaround for Errata 46 "Higher power consumption of LFRC" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/index.jsp */
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if (nrf53_errata_46())
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{
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*((volatile uint32_t *)0x5003254Cul) = 0;
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}
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/* Workaround for Errata 49 "SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/index.jsp */
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if (nrf53_errata_49())
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{
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if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk)
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{
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NRF_POWER_S->EVENTS_SLEEPENTER = 0;
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NRF_POWER_S->EVENTS_SLEEPEXIT = 0;
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}
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}
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/* Workaround for Errata 55 "Bits in RESETREAS are set when they should not be" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/index.jsp */
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if (nrf53_errata_55())
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{
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if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk){
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NRF_RESET_S->RESETREAS = ~RESET_RESETREAS_RESETPIN_Msk;
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}
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}
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/* Workaround for Errata 69 "VREGMAIN configuration is not retained in System OFF" found at the Errata document
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for your device located at https://infocenter.nordicsemi.com/index.jsp */
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if (nrf53_errata_69())
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{
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*((volatile uint32_t *)0x5000470Cul) =0x65ul;
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}
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#if defined(CONFIG_NFCT_PINS_AS_GPIOS)
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if ((NRF_UICR_S->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos))
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{
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NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC_S->READY == NVMC_READY_READY_Busy);
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NRF_UICR_S->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
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while (NRF_NVMC_S->READY == NVMC_READY_READY_Busy);
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NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC_S->READY == NVMC_READY_READY_Busy);
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NVIC_SystemReset();
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}
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#endif
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/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
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Specification to see which one). */
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#if defined (ENABLE_SWO)
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// Enable Trace And Debug peripheral
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NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
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NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
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// Set up Trace pad SPU firewall
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NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
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// Configure trace port pad
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
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// Select trace pin
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NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN;
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// Set trace port speed to 64 MHz
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NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz;
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#endif
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/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
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Specification to see which ones). */
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#if defined (ENABLE_TRACE)
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// Enable Trace And Debug peripheral
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NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
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NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
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// Set up Trace pads SPU firewall
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NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN);
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NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
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NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN);
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NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN);
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NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN);
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// Configure trace port pads
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NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE;
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// Select trace pins
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NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN;
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NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN;
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NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN;
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NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN;
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NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN;
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// Set trace port speed to 64 MHz
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NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz;
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#endif
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/* Allow Non-Secure code to run FPU instructions.
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* If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
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SCB->NSACR |= (3UL << 10);
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#endif
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/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
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* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
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* operations are not used in your code. */
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#if (__FPU_USED == 1)
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SCB->CPACR |= (3UL << 20) | (3UL << 22);
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__DSB();
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__ISB();
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#endif
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SystemCoreClockUpdate();
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}
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/*lint --flb "Leave library region" */
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