358 lines
14 KiB
ArmAsm
358 lines
14 KiB
ArmAsm
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/***********************************************************************************
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* SEGGER Microcontroller GmbH *
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* The Embedded Experts *
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***********************************************************************************
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* *
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* (c) 2014 - 2018 SEGGER Microcontroller GmbH *
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* *
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* www.segger.com Support: support@segger.com *
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* *
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***********************************************************************************
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* *
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* All rights reserved. *
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* *
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* Redistribution and use in source and binary forms, with or *
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* without modification, are permitted provided that the following *
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* conditions are met: *
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* *
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* - Redistributions of source code must retain the above copyright *
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* notice, this list of conditions and the following disclaimer. *
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* *
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* - Neither the name of SEGGER Microcontroller GmbH *
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* nor the names of its contributors may be used to endorse or *
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* promote products derived from this software without specific *
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* prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
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* DISCLAIMED. *
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* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR *
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
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* DAMAGE. *
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* *
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***********************************************************************************/
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/************************************************************************************
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* Preprocessor Definitions *
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* ------------------------ *
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* VECTORS_IN_RAM *
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* *
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* If defined, an area of RAM will large enough to store the vector table *
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* will be reserved. *
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* *
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************************************************************************************/
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.syntax unified
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.code 16
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.section .init, "ax"
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.align 0
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/************************************************************************************
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* Default Exception Handlers *
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************************************************************************************/
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.thumb_func
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.weak NMI_Handler
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NMI_Handler:
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b .
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.thumb_func
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.weak HardFault_Handler
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HardFault_Handler:
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b .
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.thumb_func
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.weak MemoryManagement_Handler
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MemoryManagement_Handler:
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b .
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.thumb_func
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.weak BusFault_Handler
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BusFault_Handler:
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b .
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.thumb_func
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.weak UsageFault_Handler
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UsageFault_Handler:
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b .
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.thumb_func
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.weak SVC_Handler
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SVC_Handler:
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b .
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.thumb_func
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.weak DebugMon_Handler
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DebugMon_Handler:
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b .
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.thumb_func
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.weak PendSV_Handler
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PendSV_Handler:
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b .
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.thumb_func
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.weak SysTick_Handler
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SysTick_Handler:
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b .
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.thumb_func
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.weak Dummy_Handler
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Dummy_Handler:
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b .
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/************************************************************************************
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* Default Interrupt Handlers *
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************************************************************************************/
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.weak CLOCK_POWER_IRQHandler
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.thumb_set CLOCK_POWER_IRQHandler, Dummy_Handler
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.weak RADIO_IRQHandler
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.thumb_set RADIO_IRQHandler, Dummy_Handler
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.weak RNG_IRQHandler
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.thumb_set RNG_IRQHandler, Dummy_Handler
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.weak GPIOTE_IRQHandler
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.thumb_set GPIOTE_IRQHandler, Dummy_Handler
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.weak WDT_IRQHandler
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.thumb_set WDT_IRQHandler, Dummy_Handler
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.weak TIMER0_IRQHandler
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.thumb_set TIMER0_IRQHandler, Dummy_Handler
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.weak ECB_IRQHandler
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.thumb_set ECB_IRQHandler, Dummy_Handler
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.weak AAR_CCM_IRQHandler
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.thumb_set AAR_CCM_IRQHandler, Dummy_Handler
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.weak TEMP_IRQHandler
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.thumb_set TEMP_IRQHandler, Dummy_Handler
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.weak RTC0_IRQHandler
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.thumb_set RTC0_IRQHandler, Dummy_Handler
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.weak IPC_IRQHandler
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.thumb_set IPC_IRQHandler, Dummy_Handler
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.weak SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
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.thumb_set SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler, Dummy_Handler
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.weak EGU0_IRQHandler
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.thumb_set EGU0_IRQHandler, Dummy_Handler
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.weak RTC1_IRQHandler
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.thumb_set RTC1_IRQHandler, Dummy_Handler
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.weak TIMER1_IRQHandler
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.thumb_set TIMER1_IRQHandler, Dummy_Handler
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.weak TIMER2_IRQHandler
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.thumb_set TIMER2_IRQHandler, Dummy_Handler
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.weak SWI0_IRQHandler
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.thumb_set SWI0_IRQHandler, Dummy_Handler
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.weak SWI1_IRQHandler
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.thumb_set SWI1_IRQHandler, Dummy_Handler
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.weak SWI2_IRQHandler
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.thumb_set SWI2_IRQHandler, Dummy_Handler
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.weak SWI3_IRQHandler
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.thumb_set SWI3_IRQHandler, Dummy_Handler
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/************************************************************************************
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* Reset Handler Extensions *
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************************************************************************************/
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.extern Reset_Handler
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.global nRFInitialize
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.extern afterInitialize
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.thumb_func
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nRFInitialize:
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b afterInitialize
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/************************************************************************************
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* Vector Table *
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************************************************************************************/
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.section .vectors, "ax"
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.align 0
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.global _vectors
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.extern __stack_end__
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_vectors:
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.word __stack_end__
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemoryManagement_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0 /*Reserved */
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.word PendSV_Handler
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.word SysTick_Handler
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/* External Interrupts */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word CLOCK_POWER_IRQHandler
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word RADIO_IRQHandler
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.word RNG_IRQHandler
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.word GPIOTE_IRQHandler
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.word WDT_IRQHandler
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.word TIMER0_IRQHandler
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.word ECB_IRQHandler
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.word AAR_CCM_IRQHandler
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.word 0 /*Reserved */
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.word TEMP_IRQHandler
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.word RTC0_IRQHandler
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.word IPC_IRQHandler
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.word SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
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.word EGU0_IRQHandler
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.word 0 /*Reserved */
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.word RTC1_IRQHandler
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.word 0 /*Reserved */
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.word TIMER1_IRQHandler
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.word TIMER2_IRQHandler
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.word SWI0_IRQHandler
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.word SWI1_IRQHandler
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.word SWI2_IRQHandler
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.word SWI3_IRQHandler
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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.word 0 /*Reserved */
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_vectors_end:
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#ifdef VECTORS_IN_RAM
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|
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.section .vectors_ram, "ax"
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.align 0
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||
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.global _vectors_ram
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||
|
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_vectors_ram:
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.space _vectors_end - _vectors, 0
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#endif
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