630 lines
23 KiB
C
630 lines
23 KiB
C
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/**
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* Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/**@file
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*
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* @defgroup ser_phy_spi_5W_hw_driver_master spi_5W_master.c
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* @{
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* @ingroup ser_phy_spi_5W_hw_driver_master
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*
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* @brief SPI_5W_RAW hardware driver.
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*/
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#include "app_error.h"
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#include "app_util_platform.h"
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#include "nrf_gpio.h"
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#include "nrf.h"
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#include "spi_5W_master.h"
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#include "ser_config_5W_app.h"
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#include "ser_phy_debug_app.h"
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#include "sdk_common.h"
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#define _static
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#define DOUBLE_BUFFERED /**< A flag for enabling double buffering. */
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#define SPI_PIN_DISCONNECTED 0xFFFFFFFF /**< A value used to the PIN deinitialization. */
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#define SPI_DEFAULT_TX_BYTE 0x00 /**< Default byte (used to clock transmission
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from slave to the master) */
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typedef struct
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{
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NRF_SPI_Type * p_nrf_spi; /**< A pointer to the NRF SPI master */
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IRQn_Type irq_type; /**< A type of NVIC IRQn */
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uint8_t * p_tx_buffer; /**< A pointer to TX buffer. */
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uint16_t tx_length; /**< A length of TX buffer. */
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uint16_t tx_index; /**< A index of the current element in the TX buffer. */
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uint8_t * p_rx_buffer; /**< A pointer to RX buffer. */
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uint16_t rx_length; /**< A length RX buffer. */
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uint16_t rx_index; /**< A index of the current element in the RX buffer. */
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uint16_t max_length; /**< Max length (Max of the TX and RX length). */
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uint16_t bytes_count;
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uint8_t pin_slave_select; /**< A pin for Slave Select. */
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spi_master_event_handler_t callback_event_handler; /**< A handler for event callback function. */
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spi_master_state_t state; /**< A state of an instance of SPI master. */
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bool start_flag;
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bool abort_flag;
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} spi_master_instance_t;
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#ifdef _SPI_5W_
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typedef enum
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{
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HOOK_STATE_DISABLED,
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HOOK_STATE_IDLE,
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HOOK_STATE_GUARDED,
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HOOK_STATE_ABORTED,
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HOOK_STATE_RESTARTED,
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HOOK_STATE_PASSING
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} spi_hook_state_t;
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_static spi_master_event_handler_t m_ser_phy_event_handler;
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_static spi_master_hw_instance_t m_spi_master_hw_instance;
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_static spi_hook_state_t m_hook_state = HOOK_STATE_DISABLED;
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#endif
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#ifdef SER_PHY_DEBUG_APP_ENABLE
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_static spi_master_raw_callback_t m_debug_callback;
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#endif
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_static spi_master_instance_t m_spi_master_instances[SPI_MASTER_HW_ENABLED_COUNT];
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static __INLINE spi_master_instance_t * spi_master_get_instance(
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const spi_master_hw_instance_t spi_master_hw_instance);
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static __INLINE void spi_master_send_recv_irq(spi_master_instance_t * const p_spi_instance);
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static __INLINE void spi_master_signal_evt(spi_master_instance_t * const p_spi_instance,
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spi_master_evt_type_t event_type,
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const uint16_t data);
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#ifdef SPI_MASTER_0_ENABLE
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/**
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* @brief SPI0 interrupt handler.
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*/
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void SPI0_TWI0_IRQHandler(void)
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{
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if (NRF_SPI0->EVENTS_READY != 0)
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{
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NRF_SPI0->EVENTS_READY = 0;
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spi_master_instance_t * p_spi_instance = spi_master_get_instance(SPI_MASTER_0);
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spi_master_send_recv_irq(p_spi_instance);
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}
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}
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#endif //SPI_MASTER_0_ENABLE
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#ifdef SPI_MASTER_1_ENABLE
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/**
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* @brief SPI0 interrupt handler.
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*/
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void SPI1_TWI1_IRQHandler(void)
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{
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if (NRF_SPI1->EVENTS_READY != 0)
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{
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NRF_SPI1->EVENTS_READY = 0;
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spi_master_instance_t * p_spi_instance = spi_master_get_instance(SPI_MASTER_1);
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spi_master_send_recv_irq(p_spi_instance);
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}
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}
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#endif //SPI_MASTER_1_ENABLE
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#if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
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/**@brief Function for getting an instance of SPI master. */
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static __INLINE spi_master_instance_t * spi_master_get_instance(
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const spi_master_hw_instance_t spi_master_hw_instance)
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{
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return &(m_spi_master_instances[(uint8_t)spi_master_hw_instance]);
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}
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/** @brief Function for initializing instance of SPI master by default values. */
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static __INLINE void spi_master_init_hw_instance(NRF_SPI_Type * p_nrf_spi,
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IRQn_Type irq_type,
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spi_master_instance_t * p_spi_instance)
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{
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APP_ERROR_CHECK_BOOL(p_spi_instance != NULL);
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p_spi_instance->p_nrf_spi = p_nrf_spi;
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p_spi_instance->irq_type = irq_type;
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p_spi_instance->p_tx_buffer = NULL;
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p_spi_instance->tx_length = 0;
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p_spi_instance->tx_index = 0;
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p_spi_instance->p_rx_buffer = NULL;
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p_spi_instance->rx_length = 0;
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p_spi_instance->rx_index = 0;
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p_spi_instance->bytes_count = 0;
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p_spi_instance->max_length = 0;
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p_spi_instance->pin_slave_select = 0;
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p_spi_instance->callback_event_handler = NULL;
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p_spi_instance->state = SPI_MASTER_STATE_DISABLED;
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p_spi_instance->abort_flag = false;
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p_spi_instance->start_flag = false;
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}
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/**@brief Function for initializing TX or RX buffer. */
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static __INLINE void spi_master_buffer_init(uint8_t * const p_buf,
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const uint16_t buf_len,
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uint8_t * * pp_buf,
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uint16_t * const p_buf_len,
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uint16_t * const p_index)
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{
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APP_ERROR_CHECK_BOOL(pp_buf != NULL);
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APP_ERROR_CHECK_BOOL(p_buf_len != NULL);
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APP_ERROR_CHECK_BOOL(p_index != NULL);
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*pp_buf = p_buf;
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*p_buf_len = (p_buf != NULL) ? buf_len : 0;
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*p_index = 0;
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}
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/**@brief Function for releasing TX or RX buffer. */
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static __INLINE void spi_master_buffer_release(uint8_t * * const pp_buf, uint16_t * const p_buf_len)
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{
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APP_ERROR_CHECK_BOOL(pp_buf != NULL);
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APP_ERROR_CHECK_BOOL(p_buf_len != NULL);
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*pp_buf = NULL;
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*p_buf_len = 0;
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}
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/**@brief Function for sending events by callback. */
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static __INLINE void spi_master_signal_evt(spi_master_instance_t * const p_spi_instance,
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spi_master_evt_type_t event_type,
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const uint16_t data)
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{
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APP_ERROR_CHECK_BOOL(p_spi_instance != NULL);
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if (p_spi_instance->callback_event_handler != NULL)
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{
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spi_master_evt_t event = {SPI_MASTER_EVT_TYPE_MAX, 0};
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event.type = event_type;
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event.data = data;
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p_spi_instance->callback_event_handler(event);
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}
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}
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/**@brief Function insert to a TX buffer another byte or two bytes (depends on flag @ref DOUBLE_BUFFERED). */
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static __INLINE void spi_master_send_initial_bytes(spi_master_instance_t * const p_spi_instance)
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{
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APP_ERROR_CHECK_BOOL(p_spi_instance != NULL);
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p_spi_instance->p_nrf_spi->TXD = ((p_spi_instance->p_tx_buffer != NULL) &&
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(p_spi_instance->tx_index < p_spi_instance->tx_length)) ?
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p_spi_instance->p_tx_buffer[p_spi_instance->tx_index] :
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SPI_DEFAULT_TX_BYTE;
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(p_spi_instance->tx_index)++;
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#ifdef DOUBLE_BUFFERED
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if (p_spi_instance->tx_index < p_spi_instance->max_length)
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{
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p_spi_instance->p_nrf_spi->TXD = ((p_spi_instance->p_tx_buffer != NULL) &&
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(p_spi_instance->tx_index < p_spi_instance->tx_length)) ?
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p_spi_instance->p_tx_buffer[p_spi_instance->tx_index] :
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SPI_DEFAULT_TX_BYTE;
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(p_spi_instance->tx_index)++;
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}
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#endif
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}
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/**@brief Function for receiving and sending data from IRQ. (The same for both IRQs). */
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static __INLINE void spi_master_send_recv_irq(spi_master_instance_t * const p_spi_instance)
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{
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uint8_t rx_byte;
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APP_ERROR_CHECK_BOOL(p_spi_instance != NULL);
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APP_ERROR_CHECK_BOOL(p_spi_instance->state == SPI_MASTER_STATE_BUSY);
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p_spi_instance->bytes_count++;
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rx_byte = p_spi_instance->p_nrf_spi->RXD;
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if (p_spi_instance->start_flag)
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{
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p_spi_instance->start_flag = false;
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spi_master_signal_evt(p_spi_instance, SPI_MASTER_EVT_FIRST_BYTE_RECEIVED, (uint16_t)rx_byte);
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}
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else if (p_spi_instance->abort_flag ) //this is tricky, but callback for SPI_MASTER_EVT_FIRST_BYTE_RECEIVED will set this flag for a first byte, which is bad because there is still byte in a buffer
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{ //and for a single byte transaction you will get XFERDONE event to restart
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p_spi_instance->abort_flag = false;
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p_spi_instance->state = SPI_MASTER_STATE_ABORTED;
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nrf_gpio_pin_set(p_spi_instance->pin_slave_select);
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spi_master_signal_evt(p_spi_instance, SPI_MASTER_EVT_TRANSFER_ABORTED, 0);
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return;
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}
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if ((p_spi_instance->p_rx_buffer != NULL) &&
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(p_spi_instance->rx_index < p_spi_instance->rx_length))
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{
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p_spi_instance->p_rx_buffer[p_spi_instance->rx_index++] = rx_byte;
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}
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if ((p_spi_instance->tx_index < p_spi_instance->max_length) && (!(p_spi_instance->abort_flag))) //do not TX if you know that there is an abort to be done - this should work for a DOUBLE BUFFERING ???
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{
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p_spi_instance->p_nrf_spi->TXD = ((p_spi_instance->p_tx_buffer != NULL) &&
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(p_spi_instance->tx_index < p_spi_instance->tx_length)) ?
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p_spi_instance->p_tx_buffer[p_spi_instance->tx_index] :
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SPI_DEFAULT_TX_BYTE;
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(p_spi_instance->tx_index)++;
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}
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if (p_spi_instance->bytes_count >= p_spi_instance->max_length)
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{
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APP_ERROR_CHECK_BOOL(p_spi_instance->bytes_count == p_spi_instance->max_length);
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nrf_gpio_pin_set(p_spi_instance->pin_slave_select);
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p_spi_instance->state = SPI_MASTER_STATE_IDLE;
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spi_master_signal_evt(p_spi_instance,
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SPI_MASTER_EVT_TRANSFER_COMPLETED,
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p_spi_instance->tx_index);
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}
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return;
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}
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#endif //defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
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/**
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* @brief Function for opening and initializing a SPI master driver. */
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uint32_t spi_master_open(const spi_master_hw_instance_t spi_master_hw_instance,
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spi_master_config_t const * const p_spi_master_config)
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{
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#if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
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VERIFY_PARAM_NOT_NULL(p_spi_master_config);
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spi_master_instance_t * p_spi_instance = spi_master_get_instance(spi_master_hw_instance);
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switch (spi_master_hw_instance)
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{
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#ifdef SPI_MASTER_0_ENABLE
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case SPI_MASTER_0:
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spi_master_init_hw_instance(NRF_SPI0, SPI0_TWI0_IRQn, p_spi_instance);
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break;
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#endif //SPI_MASTER_0_ENABLE
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#ifdef SPI_MASTER_1_ENABLE
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case SPI_MASTER_1:
|
||
|
|
spi_master_init_hw_instance(NRF_SPI1, SPI1_TWI1_IRQn, p_spi_instance);
|
||
|
|
break;
|
||
|
|
#endif //SPI_MASTER_1_ENABLE
|
||
|
|
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
//A Slave select must be set as high before setting it as output,
|
||
|
|
//because during connect it to the pin it causes glitches.
|
||
|
|
nrf_gpio_pin_set(p_spi_master_config->SPI_Pin_SS);
|
||
|
|
nrf_gpio_cfg_output(p_spi_master_config->SPI_Pin_SS);
|
||
|
|
nrf_gpio_pin_set(p_spi_master_config->SPI_Pin_SS);
|
||
|
|
|
||
|
|
//Configure GPIO
|
||
|
|
nrf_gpio_cfg_output(p_spi_master_config->SPI_Pin_SCK);
|
||
|
|
nrf_gpio_cfg_output(p_spi_master_config->SPI_Pin_MOSI);
|
||
|
|
nrf_gpio_cfg_input(p_spi_master_config->SPI_Pin_MISO, NRF_GPIO_PIN_NOPULL);
|
||
|
|
p_spi_instance->pin_slave_select = p_spi_master_config->SPI_Pin_SS;
|
||
|
|
|
||
|
|
/* Configure SPI hardware */
|
||
|
|
p_spi_instance->p_nrf_spi->PSELSCK = p_spi_master_config->SPI_Pin_SCK;
|
||
|
|
p_spi_instance->p_nrf_spi->PSELMOSI = p_spi_master_config->SPI_Pin_MOSI;
|
||
|
|
p_spi_instance->p_nrf_spi->PSELMISO = p_spi_master_config->SPI_Pin_MISO;
|
||
|
|
|
||
|
|
p_spi_instance->p_nrf_spi->FREQUENCY = p_spi_master_config->SPI_Freq;
|
||
|
|
|
||
|
|
p_spi_instance->p_nrf_spi->CONFIG =
|
||
|
|
(uint32_t)(p_spi_master_config->SPI_CPHA << SPI_CONFIG_CPHA_Pos) |
|
||
|
|
(p_spi_master_config->SPI_CPOL << SPI_CONFIG_CPOL_Pos) |
|
||
|
|
(p_spi_master_config->SPI_ORDER << SPI_CONFIG_ORDER_Pos);
|
||
|
|
|
||
|
|
|
||
|
|
/* Clear waiting interrupts and events */
|
||
|
|
p_spi_instance->p_nrf_spi->EVENTS_READY = 0;
|
||
|
|
|
||
|
|
NVIC_ClearPendingIRQ(p_spi_instance->irq_type);
|
||
|
|
NVIC_SetPriority(p_spi_instance->irq_type, APP_IRQ_PRIORITY_MID);
|
||
|
|
|
||
|
|
/* Clear event handler */
|
||
|
|
p_spi_instance->callback_event_handler = NULL;
|
||
|
|
|
||
|
|
/* Enable interrupt */
|
||
|
|
p_spi_instance->p_nrf_spi->INTENSET = (SPI_INTENSET_READY_Set << SPI_INTENCLR_READY_Pos);
|
||
|
|
NVIC_EnableIRQ(p_spi_instance->irq_type);
|
||
|
|
|
||
|
|
/* Enable SPI hardware */
|
||
|
|
p_spi_instance->p_nrf_spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
|
||
|
|
|
||
|
|
/* Change state to IDLE */
|
||
|
|
p_spi_instance->state = SPI_MASTER_STATE_IDLE;
|
||
|
|
|
||
|
|
return NRF_SUCCESS;
|
||
|
|
#else
|
||
|
|
return NRF_ERROR_NOT_SUPPORTED;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Function for closing a SPI master driver.
|
||
|
|
*/
|
||
|
|
void spi_master_close(const spi_master_hw_instance_t spi_master_hw_instance)
|
||
|
|
{
|
||
|
|
#if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
|
||
|
|
spi_master_instance_t * p_spi_instance = spi_master_get_instance(spi_master_hw_instance);
|
||
|
|
|
||
|
|
/* Disable interrupt */
|
||
|
|
NVIC_ClearPendingIRQ(p_spi_instance->irq_type);
|
||
|
|
NVIC_DisableIRQ(p_spi_instance->irq_type);
|
||
|
|
|
||
|
|
p_spi_instance->p_nrf_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
|
||
|
|
|
||
|
|
/* Set Slave Select pin as input with pull-up. */
|
||
|
|
nrf_gpio_pin_set(p_spi_instance->pin_slave_select);
|
||
|
|
nrf_gpio_cfg_input(p_spi_instance->pin_slave_select, NRF_GPIO_PIN_PULLUP);
|
||
|
|
p_spi_instance->pin_slave_select = (uint8_t)0xFF;
|
||
|
|
|
||
|
|
/* Disconnect pins from SPI hardware */
|
||
|
|
p_spi_instance->p_nrf_spi->PSELSCK = (uint32_t)SPI_PIN_DISCONNECTED;
|
||
|
|
p_spi_instance->p_nrf_spi->PSELMOSI = (uint32_t)SPI_PIN_DISCONNECTED;
|
||
|
|
p_spi_instance->p_nrf_spi->PSELMISO = (uint32_t)SPI_PIN_DISCONNECTED;
|
||
|
|
|
||
|
|
/* Reset to default values */
|
||
|
|
spi_master_init_hw_instance(NULL, (IRQn_Type)0, p_spi_instance);
|
||
|
|
#else
|
||
|
|
return;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Function for getting current state of the SPI master driver.
|
||
|
|
*/
|
||
|
|
__INLINE spi_master_state_t spi_master_get_state(
|
||
|
|
const spi_master_hw_instance_t spi_master_hw_instance)
|
||
|
|
{
|
||
|
|
#if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
|
||
|
|
spi_master_instance_t * spi_instance = spi_master_get_instance(spi_master_hw_instance);
|
||
|
|
return spi_instance->state;
|
||
|
|
#else
|
||
|
|
return SPI_MASTER_STATE_DISABLED;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Function for event handler registration.
|
||
|
|
*/
|
||
|
|
__INLINE void spi_master_evt_handler_reg(const spi_master_hw_instance_t spi_master_hw_instance,
|
||
|
|
spi_master_event_handler_t event_handler)
|
||
|
|
{
|
||
|
|
#if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
|
||
|
|
spi_master_instance_t * spi_instance = spi_master_get_instance(spi_master_hw_instance);
|
||
|
|
spi_instance->callback_event_handler = event_handler;
|
||
|
|
#else
|
||
|
|
return;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Function for transmitting data between SPI master and SPI slave.
|
||
|
|
*/
|
||
|
|
uint32_t spi_master_send_recv(const spi_master_hw_instance_t spi_master_hw_instance,
|
||
|
|
uint8_t * const p_tx_buf, const uint16_t tx_buf_len,
|
||
|
|
uint8_t * const p_rx_buf, const uint16_t rx_buf_len)
|
||
|
|
{
|
||
|
|
#if defined(SPI_MASTER_0_ENABLE) || defined(SPI_MASTER_1_ENABLE)
|
||
|
|
spi_master_instance_t * p_spi_instance = spi_master_get_instance(spi_master_hw_instance);
|
||
|
|
|
||
|
|
uint32_t err_code = NRF_SUCCESS;
|
||
|
|
uint16_t max_length = 0;
|
||
|
|
|
||
|
|
if (p_spi_instance->state == SPI_MASTER_STATE_IDLE)
|
||
|
|
{
|
||
|
|
NVIC_DisableIRQ(p_spi_instance->irq_type);
|
||
|
|
|
||
|
|
max_length = (rx_buf_len > tx_buf_len) ? rx_buf_len : tx_buf_len;
|
||
|
|
|
||
|
|
if (max_length > 0)
|
||
|
|
{
|
||
|
|
p_spi_instance->state = SPI_MASTER_STATE_BUSY;
|
||
|
|
p_spi_instance->start_flag = true; //abort_flag should set by abort and cleared only by restart
|
||
|
|
p_spi_instance->bytes_count = 0;
|
||
|
|
p_spi_instance->max_length = max_length;
|
||
|
|
spi_master_buffer_release(&(p_spi_instance->p_tx_buffer), &(p_spi_instance->tx_length));
|
||
|
|
spi_master_buffer_release(&(p_spi_instance->p_rx_buffer), &(p_spi_instance->rx_length));
|
||
|
|
/* Initialize buffers */
|
||
|
|
spi_master_buffer_init(p_tx_buf, tx_buf_len, &(p_spi_instance->p_tx_buffer),
|
||
|
|
&(p_spi_instance->tx_length), &(p_spi_instance->tx_index));
|
||
|
|
spi_master_buffer_init(p_rx_buf, rx_buf_len, &(p_spi_instance->p_rx_buffer),
|
||
|
|
&(p_spi_instance->rx_length), &(p_spi_instance->rx_index));
|
||
|
|
nrf_gpio_pin_clear(p_spi_instance->pin_slave_select);
|
||
|
|
spi_master_send_initial_bytes(p_spi_instance);
|
||
|
|
spi_master_signal_evt(p_spi_instance, SPI_MASTER_EVT_TRANSFER_STARTED, max_length);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
err_code = NRF_ERROR_INVALID_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
NVIC_EnableIRQ(p_spi_instance->irq_type);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
err_code = NRF_ERROR_BUSY;
|
||
|
|
}
|
||
|
|
|
||
|
|
return err_code;
|
||
|
|
#else
|
||
|
|
return NRF_ERROR_NOT_SUPPORTED;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef _SPI_5W_
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Function for aborting transfer
|
||
|
|
*/
|
||
|
|
uint32_t spi_master_abort(const spi_master_hw_instance_t spi_master_hw_instance)
|
||
|
|
{
|
||
|
|
spi_master_instance_t * p_spi_instance = spi_master_get_instance(spi_master_hw_instance);
|
||
|
|
|
||
|
|
NVIC_DisableIRQ(p_spi_instance->irq_type);
|
||
|
|
|
||
|
|
if (p_spi_instance->state == SPI_MASTER_STATE_BUSY)
|
||
|
|
{
|
||
|
|
//set_flag - but only when there are events pending
|
||
|
|
//ignore when in IDLE - must be able to restart a completed transfer
|
||
|
|
p_spi_instance->abort_flag = true;
|
||
|
|
}
|
||
|
|
NVIC_EnableIRQ(p_spi_instance->irq_type);
|
||
|
|
return NRF_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Function for restarting transfer
|
||
|
|
*/
|
||
|
|
uint32_t spi_master_restart(const spi_master_hw_instance_t spi_master_hw_instance)
|
||
|
|
{
|
||
|
|
spi_master_instance_t * p_spi_instance = spi_master_get_instance(spi_master_hw_instance);
|
||
|
|
|
||
|
|
NVIC_DisableIRQ(p_spi_instance->irq_type);
|
||
|
|
spi_master_signal_evt(p_spi_instance, SPI_MASTER_EVT_TRANSFER_RESTARTED, 0);
|
||
|
|
p_spi_instance->state = SPI_MASTER_STATE_BUSY;
|
||
|
|
p_spi_instance->bytes_count = 0;
|
||
|
|
p_spi_instance->tx_index = 0;
|
||
|
|
p_spi_instance->rx_index = 0;
|
||
|
|
p_spi_instance->start_flag = true;
|
||
|
|
p_spi_instance->abort_flag = false; //you should force clearing abort flag - no other way for 1 byte transfer
|
||
|
|
nrf_gpio_pin_clear(p_spi_instance->pin_slave_select);
|
||
|
|
spi_master_send_initial_bytes(p_spi_instance);
|
||
|
|
NVIC_EnableIRQ(p_spi_instance->irq_type);
|
||
|
|
|
||
|
|
return NRF_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void spi_5W_master_event_handler(spi_master_evt_t evt)
|
||
|
|
{
|
||
|
|
|
||
|
|
switch (m_hook_state)
|
||
|
|
{
|
||
|
|
case HOOK_STATE_IDLE:
|
||
|
|
|
||
|
|
if (evt.type == SPI_MASTER_EVT_TRANSFER_STARTED)
|
||
|
|
{
|
||
|
|
DEBUG_EVT_SPI_MASTER_RAW_XFER_GUARDED(0);
|
||
|
|
m_hook_state = HOOK_STATE_GUARDED;
|
||
|
|
m_ser_phy_event_handler(evt);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HOOK_STATE_GUARDED:
|
||
|
|
|
||
|
|
if (evt.type == SPI_MASTER_EVT_FIRST_BYTE_RECEIVED)
|
||
|
|
{
|
||
|
|
if (evt.data == 0)
|
||
|
|
{
|
||
|
|
DEBUG_EVT_SPI_MASTER_RAW_XFER_PASSED(0);
|
||
|
|
m_hook_state = HOOK_STATE_PASSING;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
DEBUG_EVT_SPI_MASTER_RAW_XFER_ABORTED(0);
|
||
|
|
m_hook_state = HOOK_STATE_ABORTED;
|
||
|
|
(void)spi_master_abort(m_spi_master_hw_instance);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HOOK_STATE_ABORTED:
|
||
|
|
|
||
|
|
if ((evt.type == SPI_MASTER_EVT_TRANSFER_ABORTED) ||
|
||
|
|
(evt.type == SPI_MASTER_EVT_TRANSFER_COMPLETED))
|
||
|
|
{
|
||
|
|
DEBUG_EVT_SPI_MASTER_RAW_XFER_RESTARTED(0);
|
||
|
|
m_hook_state = HOOK_STATE_RESTARTED;
|
||
|
|
(void)spi_master_restart(m_spi_master_hw_instance);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HOOK_STATE_RESTARTED:
|
||
|
|
|
||
|
|
if (evt.type == SPI_MASTER_EVT_TRANSFER_RESTARTED)
|
||
|
|
{
|
||
|
|
DEBUG_EVT_SPI_MASTER_RAW_XFER_GUARDED(0);
|
||
|
|
m_hook_state = HOOK_STATE_GUARDED;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HOOK_STATE_PASSING:
|
||
|
|
|
||
|
|
if (evt.type == SPI_MASTER_EVT_TRANSFER_COMPLETED)
|
||
|
|
{
|
||
|
|
m_hook_state = HOOK_STATE_IDLE;
|
||
|
|
m_ser_phy_event_handler(evt); //this is the only way to get a signal from complete transaction
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void spi_5W_master_evt_handler_reg(const spi_master_hw_instance_t spi_master_hw_instance,
|
||
|
|
spi_master_event_handler_t event_handler)
|
||
|
|
{
|
||
|
|
m_ser_phy_event_handler = event_handler;
|
||
|
|
m_spi_master_hw_instance = spi_master_hw_instance;
|
||
|
|
m_hook_state = HOOK_STATE_IDLE;
|
||
|
|
spi_master_evt_handler_reg(spi_master_hw_instance, spi_5W_master_event_handler);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/** @} */
|