214 lines
10 KiB
C
214 lines
10 KiB
C
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/**
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* Copyright (c) 2020, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef NRF21540_SPI_H_
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#define NRF21540_SPI_H_
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#include <stdbool.h>
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#include <stdint.h>
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#include "nrfx_spim.h"
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#include "nrf21540_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief nRF21540 SPI interface parameters defines.
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*/
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#define NRF21540_SPI_LENGTH_BYTES 2 ///< SPI tx/rx buffer size in bytes.
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#define NRF21540_SPI_COMMAND_ADDR_BYTE 0 ///< Position of command field in SPI frame.
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#define NRF21540_SPI_DATA_BYTE 1 ///< Position of data field in SPI frame.
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#define NRF21540_SPI_COMMAND_Pos 6 ///< Command code bit-position in command field.
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#define NRF21540_SPI_REG_Pos 0 ///< Register address bit-position in command field.
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#define NRF21540_SPI_COMMAND_NOP 0x00 ///< 'NOP' command code.
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#define NRF21540_SPI_COMMAND_READ 0x02 ///< 'READ' command code.
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#define NRF21540_SPI_COMMAND_WRITE 0x03 ///< 'WRITE' command code.
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/**@brief CONFREG0 register bitfields.
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*/
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#define NRF21540_BITS_CONFREG0_TX_EN_Pos 0 ///< Position of TX_EN field.
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#define NRF21540_BITS_CONFREG0_TX_EN_Msk (1 << NRF21540_BITS_CONFREG0_TX_EN_Pos) ///< Bit mask of TX_EN field.
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#define NRF21540_BITS_CONFREG0_TX_EN_Disable 0 ///< Disable TX mode.
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#define NRF21540_BITS_CONFREG0_TX_EN_Enable 1 ///< Enable TX mode.
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#define NRF21540_BITS_CONFREG0_MODE_Pos 1 ///< Position of MODE field.
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#define NRF21540_BITS_CONFREG0_MODE_Msk (1 << NRF21540_BITS_CONFREG0_MODE_Pos) ///< Bit mask of MODE field.
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#define NRF21540_BITS_CONFREG0_MODE_0 0 ///< Selects MODE 0.
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#define NRF21540_BITS_CONFREG0_MODE_1 1 ///< Selects MODE 1.
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#define NRF21540_BITS_CONFREG0_TX_GAIN_Pos 2 ///< Position of TX_GAIN field.
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#define NRF21540_BITS_CONFREG0_TX_GAIN_Msk (0x1F << NRF21540_BITS_CONFREG0_TX_GAIN_Pos) ///< Bit mask of TX_GAIN field.
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#define NRF21540_BITS_CONFREG0_TX_GAIN_Min 0 ///< Minimum TX_GAIN register value
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#define NRF21540_BITS_CONFREG0_TX_GAIN_Max 31 ///< Maximum TX_GAIN register value
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/**@brief CONFREG1 register bitfields.
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*/
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#define NRF21540_BITS_CONFREG1_RX_EN_Pos 0 ///< Position of RX_EN field.
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#define NRF21540_BITS_CONFREG1_RX_EN_Msk (1 << NRF21540_BITS_CONFREG1_RX_EN_Pos) ///< Bit mask of TX_EN field.
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#define NRF21540_BITS_CONFREG1_RX_EN_Disable 0 ///< Disable RX mode.
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#define NRF21540_BITS_CONFREG1_RX_EN_Enable 1 ///< Enable RX mode.
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#define NRF21540_BITS_CONFREG1_UICR_EN_Pos 2 ///< Position of UICR_EN field.
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#define NRF21540_BITS_CONFREG1_UICR_EN_Msk (1 << NRF21540_BITS_CONFREG1_UICR_EN_Pos) ///< Bit mask of UICR_EN field.
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#define NRF21540_BITS_CONFREG1_UICR_EN_Disable 0 ///< Disable UICR program mode.
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#define NRF21540_BITS_CONFREG1_UICR_EN_Enable 1 ///< Enable UICR program mode.
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#define NRF21540_BITS_CONFREG1_KEY_Pos 4 ///< Position of KEY field.
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#define NRF21540_BITS_CONFREG1_KEY_Msk (0x0F << NRF21540_BITS_CONFREG1_KEY_Pos) ///< Bit mask of KEY field.
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#define NRF21540_BITS_CONFREG1_KEY_Enter 15 ///< Enter UICR program mode.
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#define NRF21540_BITS_CONFREG1_KEY_Leave 0 ///< Leave UICR program mode.
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/**@brief CONFREG2 register bitfields.
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*/
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#define NRF21540_BITS_CONFREG2_POUTA_UICR_Pos 0 ///< Position of POUTA_UICR field.
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#define NRF21540_BITS_CONFREG2_POUTA_UICR_Msk (0x1F << NRF21540_BITS_CONFREG2_POUTA_UICR_Pos) ///< Bit mask of POUTA_UICR field.
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#define NRF21540_BITS_CONFREG2_POUTA_UICR_Min 0 ///< Minimum POUTA_UICR register value
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#define NRF21540_BITS_CONFREG2_POUTA_UICR_Max 31 ///< Maximum POUTA_UICR register value
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#define NRF21540_BITS_CONFREG2_POUTA_SEL_Pos 5 ///< Position of POUTA_SEL field.
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#define NRF21540_BITS_CONFREG2_POUTA_SEL_Msk (1 << NRF21540_BITS_CONFREG2_POUTA_SEL_Pos) ///< Bit mask of POUTA_SEL field.
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#define NRF21540_BITS_CONFREG2_POUTA_SEL_PROD 0 ///< Initialize TX_GAIN register with 20dBm value.
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#define NRF21540_BITS_CONFREG2_POUTA_SEL_UICR 1 ///< Initialize TX_GAIN register with POUTA_UICR value.
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#define NRF21540_BITS_CONFREG2_WR_UICR_Pos 7 ///< Position of WR_UICR field.
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#define NRF21540_BITS_CONFREG2_WR_UICR_Msk (1 << NRF21540_BITS_CONFREG2_WR_UICR_Pos) ///< Bit mask of WR_UICR field.
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#define NRF21540_BITS_CONFREG2_WR_UICR_IDLE 0 ///< EFUSE idle .
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#define NRF21540_BITS_CONFREG2_WR_UICR_WRITE 1 ///< EFUSE write.
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/**@brief CONFREG3 register bitfields.
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*/
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#define NRF21540_BITS_CONFREG3_POUTB_UICR_Pos 0 ///< Position of POUTB_UICR field.
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#define NRF21540_BITS_CONFREG3_POUTB_UICR_Msk (0x1F << NRF21540_BITS_CONFREG3_POUTB_SEL_Pos) ///< Bit mask of POUTB_UICR field.
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#define NRF21540_BITS_CONFREG3_POUTB_UICR_Min 0 ///< Minimum POUTB_UICR register value
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#define NRF21540_BITS_CONFREG3_POUTB_UICR_Max 31 ///< Maximum POUTB_UICR register value
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#define NRF21540_BITS_CONFREG3_POUTB_SEL_Pos 5 ///< Position of POUTB_SEL field.
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#define NRF21540_BITS_CONFREG3_POUTB_SEL_Msk (1 << NRF21540_BITS_CONFREG3_POUTB_SEL_Pos) ///< Bit mask of POUTB_SEL field.
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#define NRF21540_BITS_CONFREG3_POUTB_SEL_PROD 0 ///< Initialize TX_GAIN register with 20dBm value.
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#define NRF21540_BITS_CONFREG3_POUTB_SEL_UICR 1 ///< Initialize TX_GAIN register with POUTB_UICR value.
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/**@brief PARTNUMBER register bitfields.
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*/
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#define NRF21540_PARTNUMBER_PARTNUMBER_Pos 0 ///< Position of PARTNUMBER field.
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#define NRF21540_PARTNUMBER_PARTNUMBER_Msk (0xFF << NRF21540_PARTNUMBER_PARTNUMBER_Pos) ///< Bit mask of PARTNUMBER field.
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/**@brief HW_REVISON register bitfields.
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*/
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#define NRF21540_HW_REVISON_HW_REVISION_Pos 4 ///< Position of HW_REVISON field.
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#define NRF21540_HW_REVISON_HW_REVISION_Msk (0xF << NRF21540_HW_REVISON_HW_REVISION_Pos) ///< Bit mask of HW_REVISON field.
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/**@brief HW_ID0 register bitfields.
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*/
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#define NRF21540_HW_ID0_Pos 0 ///< Position of HW_ID0 field.
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#define NRF21540_HW_ID0_Msk (0xFF << NRF21540_HW_ID0_Pos) ///< Bit mask of HW_ID0 field.
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/**@brief HW_ID1 register bitfields.
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*/
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#define NRF21540_HW_ID1_Pos 0 ///< Position of HW_ID1 field.
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#define NRF21540_HW_ID1_Msk (0xFF << NRF21540_HW_ID1_Pos) ///< Bit mask of HW_ID1 field.
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/**@brief nRF21540 internal registers.
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*/
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typedef enum
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{
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NRF21540_REG_CONFREG0 = 0x00, ///< CONFREG0 register address.
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NRF21540_REG_CONFREG1 = 0x01, ///< CONFREG1 register address.
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NRF21540_REG_CONFREG2 = 0x02, ///< CONFREG2 register address.
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NRF21540_REG_CONFREG3 = 0x03, ///< CONFREG3 register address.
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NRF21540_REG_PARTNUMBER = 0x14, ///< PARTNUMBER register address.
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NRF21540_REG_HW_REVISION = 0x15, ///< HW_REVISION register address.
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NRF21540_REG_HW_ID0 = 0x16, ///< HW_ID0 register address.
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NRF21540_REG_HW_ID1 = 0x17, ///< HW_ID1 register address.
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} nrf21540_reg_t;
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/**@brief Function initializes SPI interface.
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*
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* @return NRF_ERROR_INTERNAL when SPIM driver initialization error occured.
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* NRF_ERROR_INVALID_STATE when nRF21540's state isn't proper
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* to perform the operation.
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* NRF_SUCCESS on success.
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*/
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ret_code_t nrf21540_spi_init(void);
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/**@brief Function returns address of task which triggers SPI transfer.
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*
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* @return address of appropriate task.
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*/
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uint32_t nrf21540_spim_trx_task_start_address_get(void);
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/**@brief Function configures the chip and peripherals for TX/RX transfer purpose.
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*
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* @details It can enable/disable RX/TX transfers.
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*
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* @param[in] dir Direction of the radio transmission. See @ref nrf21540_trx_t.
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* @param[in] required_state State of RX/TX transfer. See @ref nrf21540_bool_state_t.
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* chosen transfer type.
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*/
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void nrf21540_spim_for_trx_configure(nrf21540_trx_t dir, nrf21540_bool_state_t required_state);
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/**@brief Function choses one of predefined power modes in nRF21540.
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*
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* @details Refer to nRF21540 Objective Product Specification, section: TX power control.
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*
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* @param[in] mode Power mode. See @ref nrf21540_pwr_mode_t.
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* @return NRF_ERROR_INVALID_PARAM when invalid argument given.
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* NRF_SUCCESS on success.
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*/
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ret_code_t nrf21540_spi_pwr_mode_set(nrf21540_pwr_mode_t mode);
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/**@brief Function sets nRF21540 power state by driving PDN pin.
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*
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* @param[in] state Required PDN pin state.
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* @param[in] mode Execution mode. See @ref nrf21540_execution_mode_t.
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* @return NRF_ERROR_INVALID_PARAM when invalid argument given.
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* NRF_ERROR_INVALID_STATE when nRF21540's state isn't proper
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* to perform the operation (@sa nrf21540_state_t).
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* NRF_ERROR_INTERNAL when driver is in error state.
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* Reinitialization is required.
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* NRF_SUCCESS on success.
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*/
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ret_code_t nrf21540_pdn_drive(bool state, nrf21540_execution_mode_t mode);
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#ifdef __cplusplus
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}
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#endif
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#endif // NRF21540_SPI_H_
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