270 lines
10 KiB
C
270 lines
10 KiB
C
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/**
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* Copyright (c) 2020, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "nrf21540_spi.h"
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#include <string.h>
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#include "nrf_assert.h"
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#include "boards.h"
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#include "nrf_ppi.h"
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#include "nrf21540_defs.h"
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#include "nrf_timer.h"
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#if NRF21540_USE_SPI_MANAGEMENT
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static uint8_t m_spi_tx_data[NRF21540_SPI_LENGTH_BYTES]; ///< SPI tx buffer.
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static uint8_t m_spi_rx_data[NRF21540_SPI_LENGTH_BYTES]; ///< SPI rx buffer.
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static volatile bool m_spi_xfer_done; ///< Flag indicates that SPI completed the transfer.
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/**@brief Structure keeps content of important registers of nRF21540.
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*
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* @details Driver keeps this data because it needs to operate at single bits
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* included in these registers (otherwise it should read it content
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* during every operation).
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*/
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static struct {
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uint8_t CONFREG0; ///< CONFREG0 register's content.
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uint8_t CONFREG1; ///< CONFREG1 register's content.
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} m_confreg_statics;
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static const nrfx_spim_t spi = NRFX_SPIM_INSTANCE(NRF21540_SPIM_NO); /**< SPI instance. */
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/**@brief Function waits for SPI transfer has finished
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*
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* @details Used in blocking mode transfer
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*/
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static inline void wait_for_transfer_end(void)
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{
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while (!m_spi_xfer_done)
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{}
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m_spi_xfer_done = false;
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}
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/**@brief Handler called by nrfx driver when SPI event occurs.
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*
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* @param[in] p_event Event which triggers the handler.
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* @param[in] p_context Context.
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*/
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static void spim_event_handler(nrfx_spim_evt_t const *p_event, void *p_context)
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{
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m_spi_xfer_done = true;
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}
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/**@brief Function reads the content of nRF21540 chip register.
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*
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* @details Preparation of read register operation. Every register has one byte size.
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*
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* @param[in] reg Register address to read.
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* @param[in] mode if NRF21540_EXEC_MODE_BLOCKING the function will wait for data
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* received.
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* @param[in] start_now if enabled, transmision immediately initialized,
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* otherwise transfer will be triggered by external event.
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*/
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static uint8_t spi_reg_read(nrf21540_reg_t reg, nrf21540_execution_mode_t mode, bool start_now)
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{
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ASSERT(!(mode == NRF21540_EXEC_MODE_BLOCKING && start_now == false));
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nrfx_spim_xfer_desc_t xfer_desc = NRFX_SPIM_XFER_TRX(m_spi_tx_data,
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NRF21540_SPI_LENGTH_BYTES,
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m_spi_rx_data,
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NRF21540_SPI_LENGTH_BYTES);
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m_spi_tx_data[NRF21540_SPI_COMMAND_ADDR_BYTE] =
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(NRF21540_SPI_COMMAND_READ << NRF21540_SPI_COMMAND_Pos) | (reg << NRF21540_SPI_REG_Pos);
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(void)nrfx_spim_xfer(&spi, &xfer_desc, 0);
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if (mode == NRF21540_EXEC_MODE_BLOCKING)
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{
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wait_for_transfer_end();
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}
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return m_spi_rx_data[NRF21540_SPI_DATA_BYTE];
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}
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/**@brief Function writes the content of nRF21540 chip register.
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*
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* @details Preparation of data to send. Every register has one byte size.
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*
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* @param[in] reg Register address to write.
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* @param[in] data Data to write.
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* @param[in] mode if NRF21540_EXEC_MODE_BLOCKING the function will wait for transfer
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* finished after sending data.
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* @param[in] start_now if enabled, transmision immediately initialized,
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* otherwise transfer will be triggered by external event.
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*/
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static void spi_reg_write(nrf21540_reg_t reg, uint8_t data, nrf21540_execution_mode_t mode, bool start_now)
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{
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ASSERT(!(mode == NRF21540_EXEC_MODE_BLOCKING && start_now == false));
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nrfx_spim_xfer_desc_t xfer_desc = NRFX_SPIM_XFER_TRX(m_spi_tx_data,
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NRF21540_SPI_LENGTH_BYTES,
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m_spi_rx_data,
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NRF21540_SPI_LENGTH_BYTES);
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m_spi_tx_data[NRF21540_SPI_COMMAND_ADDR_BYTE] =
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(NRF21540_SPI_COMMAND_WRITE << NRF21540_SPI_COMMAND_Pos) | (reg << NRF21540_SPI_REG_Pos);
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m_spi_tx_data[NRF21540_SPI_DATA_BYTE] = data;
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uint32_t flags = start_now ? 0 : NRFX_SPIM_FLAG_HOLD_XFER;
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(void)nrfx_spim_xfer(&spi, &xfer_desc, flags);
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if (mode == NRF21540_EXEC_MODE_BLOCKING)
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{
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wait_for_transfer_end();
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}
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}
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/**@brief Function reads content of important nRF21540's registers and stores
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* it to dedicated structure (@ref m_confreg_statics).
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*
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* @return Return NRF based error code.
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*/
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static ret_code_t m_confreg_statics_content_update(void)
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{
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ret_code_t ret = nrf21540_pdn_drive(true, NRF21540_EXEC_MODE_BLOCKING);
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if (ret != NRF_SUCCESS)
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{
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return ret;
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}
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m_confreg_statics.CONFREG0 = spi_reg_read(NRF21540_REG_CONFREG0,
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NRF21540_EXEC_MODE_BLOCKING, true);
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m_confreg_statics.CONFREG1 = spi_reg_read(NRF21540_REG_CONFREG1,
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NRF21540_EXEC_MODE_BLOCKING, true);
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return nrf21540_pdn_drive(false, NRF21540_EXEC_MODE_BLOCKING);
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}
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ret_code_t nrf21540_spi_init(void)
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{
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ret_code_t ret;
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nrfx_spim_config_t spi_config = NRFX_SPIM_DEFAULT_CONFIG;
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spi_config.frequency = NRF_SPIM_FREQ_4M;
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spi_config.ss_pin = NRF21540_CS_PIN;
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spi_config.miso_pin = NRF21540_MISO_PIN;
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spi_config.mosi_pin = NRF21540_MOSI_PIN;
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spi_config.sck_pin = NRF21540_CLK_PIN;
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spi_config.ss_active_high = false;
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ret = nrfx_spim_init(&spi, &spi_config, spim_event_handler, NULL);
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if (ret != NRFX_SUCCESS)
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{
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return NRF_ERROR_INTERNAL;
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}
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return m_confreg_statics_content_update();
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}
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/**@brief Function enables or disables nRF21540 TX mode.
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*
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* @details Preparation of appropriate register content and tranfer initialization.
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*
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* @param[in] state NRF21540_DISABLE/NRF21540_ENABLE causes TX mode disabled/enabled.
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*/
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static void tx_en_drive(nrf21540_bool_state_t state)
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{
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uint8_t reg_val;
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if (state == NRF21540_ENABLE)
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{
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reg_val = m_confreg_statics.CONFREG0 | NRF21540_BITS_CONFREG0_TX_EN_Enable;
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}
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else
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{
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reg_val = m_confreg_statics.CONFREG0 &(~NRF21540_BITS_CONFREG0_TX_EN_Enable);
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}
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spi_reg_write(NRF21540_REG_CONFREG0, reg_val, NRF21540_EXEC_MODE_NON_BLOCKING, false);
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}
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/**@brief Function enables or disables nRF21540 RX mode.
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*
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* @details Preparation of appropriate register content and tranfer initialization.
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*
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* @param[in] state NRF21540_DISABLE/NRF21540_ENABLE causes RX mode disabled/enabled.
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*/
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static void rx_en_drive(nrf21540_bool_state_t state)
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{
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uint8_t reg_val;
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if (state == NRF21540_ENABLE)
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{
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reg_val = m_confreg_statics.CONFREG1 | NRF21540_BITS_CONFREG1_RX_EN_Enable;
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}
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else
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{
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reg_val = m_confreg_statics.CONFREG1 &(~NRF21540_BITS_CONFREG1_RX_EN_Disable);
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}
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spi_reg_write(NRF21540_REG_CONFREG1, reg_val, NRF21540_EXEC_MODE_NON_BLOCKING, false);
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}
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inline uint32_t nrf21540_spim_trx_task_start_address_get(void)
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{
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return nrfx_spim_start_task_get(&spi);
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}
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void nrf21540_spim_for_trx_configure(nrf21540_trx_t dir, nrf21540_bool_state_t required_state)
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{
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if (dir == NRF21540_TX)
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{
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tx_en_drive(required_state);
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}
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else
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{
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rx_en_drive(required_state);
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}
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if (required_state == NRF21540_ENABLE)
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{
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uint32_t task_start_address = nrfx_spim_start_task_get(&spi);
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nrf_ppi_channel_endpoint_setup(NRF21540_TRX_PPI_CHANNEL,
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(uint32_t)nrf_timer_event_address_get(NRF21540_TIMER,
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NRF21540_TIMER_CC_PD_PG_EVENT),
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task_start_address);
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nrf_ppi_channel_enable(NRF21540_TRX_PPI_CHANNEL);
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}
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}
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ret_code_t nrf21540_spi_pwr_mode_set(nrf21540_pwr_mode_t mode)
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{
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if (mode == NRF21540_PWR_MODE_A)
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{
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spi_reg_write(NRF21540_REG_CONFREG0, NRF21540_BITS_CONFREG0_MODE_0,
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NRF21540_EXEC_MODE_BLOCKING, true);
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}
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else if (mode == NRF21540_PWR_MODE_B)
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{
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spi_reg_write(NRF21540_REG_CONFREG0, NRF21540_BITS_CONFREG0_MODE_1,
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NRF21540_EXEC_MODE_BLOCKING, true);
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}
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else
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{
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return NRF_ERROR_INVALID_PARAM;
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}
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return NRF_SUCCESS;
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}
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#endif /*NRF21540_USE_SPI_MANAGEMENT*/
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