167 lines
8.5 KiB
C
167 lines
8.5 KiB
C
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/**************************************************************************************
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* Copyright (c) 2016-2017, ARM Limited or its affiliates. All rights reserved *
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* *
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* This file and the related binary are licensed under the following license: *
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* *
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* ARM Object Code and Header Files License, v1.0 Redistribution. *
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* *
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* Redistribution and use of object code, header files, and documentation, without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1) Redistributions must reproduce the above copyright notice and the *
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* following disclaimer in the documentation and/or other materials *
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* provided with the distribution. *
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* *
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* 2) Unless to the extent explicitly permitted by law, no reverse *
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* engineering, decompilation, or disassembly of is permitted. *
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* *
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* 3) Redistribution and use is permitted solely for the purpose of *
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* developing or executing applications that are targeted for use *
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* on an ARM-based product. *
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* *
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* DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
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* CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT *
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* NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, *
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE *
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED *
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR *
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING *
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS *
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
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**************************************************************************************/
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/*!
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* @file
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* @brief Macro definitions for accessing ARM TrustZone CryptoCell register space.
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*/
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#ifndef _SSI_REGS_H_
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#define _SSI_REGS_H_
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#include "ssi_bitops.h"
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/* Register Offset macro */
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#define SASI_REG_OFFSET(unit_name, reg_name) \
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(DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET)
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#define SASI_REG_BIT_SHIFT(reg_name, field_name) \
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(DX_ ## reg_name ## _ ## field_name ## _BIT_SHIFT)
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/* Register Offset macros (from registers base address in host) */
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#if defined(DX_CC_REE) || defined(DX_CC_TEE) || defined(DX_CONFIG_IOT_SUPPORTED)
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#include "dx_reg_base_host.h"
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/* Indexed GPR offset macros - note the (not original) preprocessor tricks...*/
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/* (Using the macro without the "_" prefix is allowed with another macro *
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* as the gpr_idx) */
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#define _SEP_HOST_GPR_REG_OFFSET(gpr_idx) \
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SASI_REG_OFFSET(HOST_RGF, HOST_SEP_HOST_GPR ## gpr_idx)
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#define SEP_HOST_GPR_REG_OFFSET(gpr_idx) _SEP_HOST_GPR_REG_OFFSET(gpr_idx)
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#define _HOST_SEP_GPR_REG_OFFSET(gpr_idx) \
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SASI_REG_OFFSET(HOST_RGF, HOST_HOST_SEP_GPR ## gpr_idx)
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#define HOST_SEP_GPR_REG_OFFSET(gpr_idx) _HOST_SEP_GPR_REG_OFFSET(gpr_idx)
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/* GPR IRQ bit shift/mask by GPR index */
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#define _SEP_HOST_GPR_IRQ_SHIFT(gpr_idx) \
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DX_HOST_IRR_SEP_HOST_GPR ## gpr_idx ## _INT_BIT_SHIFT
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#define SEP_HOST_GPR_IRQ_SHIFT(gpr_idx) \
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_SEP_HOST_GPR_IRQ_SHIFT(gpr_idx)
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#define SEP_HOST_GPR_IRQ_MASK(gpr_idx) \
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(1 << SEP_HOST_GPR_IRQ_CAUSE_SHIFT(gpr_idx))
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/* Read-Modify-Write a field of a register */
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#define MODIFY_REGISTER_FLD(unitName, regName, fldName, fldVal) \
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do { \
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uint32_t regVal; \
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regVal = READ_REGISTER(SASI_REG_ADDR(unitName, regName)); \
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SASI_REG_FLD_SET(unitName, regName, fldName, regVal, fldVal); \
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WRITE_REGISTER(SASI_REG_ADDR(unitName, regName), regVal); \
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} while (0)
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#elif defined(DX_CC_SEP)
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#include "dx_reg_base_sep.h"
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/* We only provide this macro for SEP code because other platforms require usage
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of (mapping base + offset), i.e., use of SASI_REG_OFFSET */
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/* PLEASE AVOID USING THIS MACRO FOR NEW SEP CODE. USE THE OFFSET MACROS. */
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#define SASI_REG_ADDR(unit_name, reg_name) \
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(DX_BASE_CC_PERIF + DX_BASE_ ## unit_name + \
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DX_ ## reg_name ## _REG_OFFSET)
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/* Indexed GPR address macros - note the (not original) preprocessor tricks...*/
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/* (Using the macro without the "_" prefix is allowed with another macro *
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* as the gpr_idx) */
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#define _SEP_HOST_GPR_REG_ADDR(gpr_idx) \
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SASI_REG_ADDR(SEP_RGF, SEP_SEP_HOST_GPR ## gpr_idx)
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#define SEP_HOST_GPR_REG_ADDR(gpr_idx) _SEP_HOST_GPR_REG_ADDR(gpr_idx)
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#define _HOST_SEP_GPR_REG_ADDR(gpr_idx) \
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SASI_REG_ADDR(SEP_RGF, SEP_HOST_SEP_GPR ## gpr_idx)
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#define HOST_SEP_GPR_REG_ADDR(gpr_idx) _HOST_SEP_GPR_REG_ADDR(gpr_idx)
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#else
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#error Execution domain is not DX_CC_SEP/DX_CC_REE/DX_CC_TEE/DX_CONFIG_IOT_SUPPORTED
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#endif
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/* Registers address macros for ENV registers (development FPGA only) */
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#ifdef DX_BASE_ENV_REGS
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#ifndef DX_CC_SEP /* Irrelevant for SeP code */
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/* This offset should be added to mapping address of DX_BASE_ENV_REGS */
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#define SASI_ENV_REG_OFFSET(reg_name) (DX_ENV_ ## reg_name ## _REG_OFFSET)
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#endif
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#endif /*DX_BASE_ENV_REGS*/
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/* Bit fields access */
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#define SASI_REG_FLD_GET(unit_name, reg_name, fld_name, reg_val) \
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(DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \
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reg_val /*!< \internal Optimization for 32b fields */ : \
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BITFIELD_GET(reg_val, DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
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DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
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/* Bit fields access */
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#define SASI2_REG_FLD_GET(unit_name, reg_name, fld_name, reg_val) \
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(SASI_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \
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reg_val /*!< \internal Optimization for 32b fields */ : \
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BITFIELD_GET(reg_val, SASI_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
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SASI_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
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#define SASI_REG_FLD_SET( \
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unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \
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do { \
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if (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \
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reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\
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else \
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BITFIELD_SET(reg_shadow_var, \
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DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
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DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \
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new_fld_val); \
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} while (0)
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#define SASI2_REG_FLD_SET( \
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unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \
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do { \
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if (SASI_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \
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reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\
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else \
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BITFIELD_SET(reg_shadow_var, \
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SASI_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
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SASI_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \
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new_fld_val); \
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} while (0)
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/* Usage example:
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uint32_t reg_shadow = READ_REGISTER(SASI_REG_ADDR(CRY_KERNEL,AES_CONTROL));
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SASI_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3);
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SASI_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1);
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WRITE_REGISTER(SASI_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow);
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*/
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#endif /*_SSI_REGS_H_*/
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