445 lines
16 KiB
C
445 lines
16 KiB
C
/*
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@file w5500.h
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*/
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#ifndef _W5500_H_
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#define _W5500_H_
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#include "types.h"
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/**
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@brief Mode Register address
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* W5500 SPI Frame consists of 16bits Offset Address in Address Phase,
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* 8bits Control Phase and N bytes Data Phase.
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* 0 8 16 24 ~
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* |----------------|----------------|----------------|----------------------
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* | 16bit offset Address | Control Bits | Data Phase
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*
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* The 8bits Control Phase is reconfigured with Block Select bits (BSB[4:0]),
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* Read/Write Access Mode bit (RWB) and SPI Operation Mode (OM[1:0]).
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* Block Select bits select a block as like common register, socket register, tx buffer and tx buffer.
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* Address value is defined as 16bit offset Address, BSB[4:0] and the three bits of zero-padding.(The RWB and OM [1:0] are '0 'padding)
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* Please, refer to W5500 datasheet for more detail about Memory Map.
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*
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*/
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/**
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@brief Mode Register address
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*/
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#define MR (0x000000)
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/**
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@brief Gateway IP Register address
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*/
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#define GAR0 (0x000100)
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#define GAR1 (0x000200)
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#define GAR2 (0x000300)
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#define GAR3 (0x000400)
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/**
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@brief Subnet mask Register address
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*/
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#define SUBR0 (0x000500)
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#define SUBR1 (0x000600)
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#define SUBR2 (0x000700)
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#define SUBR3 (0x000800)
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/**
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@brief Source MAC Register address
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*/
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#define SHAR0 (0x000900)
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#define SHAR1 (0x000A00)
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#define SHAR2 (0x000B00)
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#define SHAR3 (0x000C00)
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#define SHAR4 (0x000D00)
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#define SHAR5 (0x000E00)
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/**
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@brief Source IP Register address
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*/
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#define SIPR0 (0x000F00)
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#define SIPR1 (0x001000)
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#define SIPR2 (0x001100)
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#define SIPR3 (0x001200)
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/**
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@brief set Interrupt low level timer register address
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*/
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#define INTLEVEL0 (0x001300)
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#define INTLEVEL1 (0x001400)
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/**
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@brief Interrupt Register
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*/
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#define IR (0x001500)
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/**
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@brief Interrupt mask register
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*/
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#define IMR (0x001600)
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#define IM_IR7 0x80
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#define IM_IR6 0x40
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#define IM_IR5 0x20
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#define IM_IR4 0x10
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/**
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@brief Socket Interrupt Register
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*/
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#define SIR (0x001700)
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/**
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@brief Socket Interrupt Mask Register
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*/
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#define SIMR (0x001800)
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#define S7_IMR 0x80
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#define S6_IMR 0x40
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#define S5_IMR 0x20
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#define S4_IMR 0x10
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#define S3_IMR 0x08
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#define S2_IMR 0x04
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#define S1_IMR 0x02
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#define S0_IMR 0x01
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/**
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@brief Timeout register address( 1 is 100us )
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*/
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#define RTR0 (0x001900)
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#define RTR1 (0x001A00)
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/**
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@brief Retry count reigster
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*/
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#define WIZ_RCR (0x001B00)
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/**
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@briefPPP LCP Request Timer register in PPPoE mode
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*/
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#define PTIMER (0x001C00)
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/**
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@brief PPP LCP Magic number register in PPPoE mode
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*/
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#define PMAGIC (0x001D00)
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/**
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@brief PPP Destination MAC Register address
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*/
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#define PDHAR0 (0x001E00)
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#define PDHAR1 (0x001F00)
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#define PDHAR2 (0x002000)
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#define PDHAR3 (0x002100)
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#define PDHAR4 (0x002200)
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#define PDHAR5 (0x002300)
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/**
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@brief PPP Session Identification Register
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*/
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#define PSID0 (0x002400)
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#define PSID1 (0x002500)
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/**
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@brief PPP Maximum Segment Size(MSS) register
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*/
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#define PMR0 (0x002600)
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#define PMR1 (0x002700)
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/**
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@brief Unreachable IP register address in UDP mode
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*/
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#define UIPR0 (0x002800)
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#define UIPR1 (0x002900)
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#define UIPR2 (0x002A00)
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#define UIPR3 (0x002B00)
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/**
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@brief Unreachable Port register address in UDP mode
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*/
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#define UPORT0 (0x002C00)
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#define UPORT1 (0x002D00)
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/**
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@brief PHY Configuration Register
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*/
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#define PHYCFGR (0x002E00)
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#define RST_PHY 0x80
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#define OPMODE 0x40
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#define DPX 0x04
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#define SPD 0x02
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#define LINK 0x01
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/**
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@brief chip version register address
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*/
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#define VERSIONR (0x003900)
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/**
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@brief socket Mode register
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*/
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#define Sn_MR(ch) (0x000008 + (ch<<5))
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/**
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@brief channel Sn_CR register
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*/
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#define Sn_CR(ch) (0x000108 + (ch<<5))
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/**
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@brief channel interrupt register
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*/
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#define Sn_IR(ch) (0x000208 + (ch<<5))
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/**
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@brief channel status register
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*/
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#define Sn_SR(ch) (0x000308 + (ch<<5))
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/**
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@brief source port register
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*/
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#define Sn_PORT0(ch) (0x000408 + (ch<<5))
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#define Sn_PORT1(ch) (0x000508 + (ch<<5))
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/**
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@brief Peer MAC register address
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*/
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#define Sn_DHAR0(ch) (0x000608 + (ch<<5))
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#define Sn_DHAR1(ch) (0x000708 + (ch<<5))
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#define Sn_DHAR2(ch) (0x000808 + (ch<<5))
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#define Sn_DHAR3(ch) (0x000908 + (ch<<5))
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#define Sn_DHAR4(ch) (0x000A08 + (ch<<5))
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#define Sn_DHAR5(ch) (0x000B08 + (ch<<5))
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/**
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@brief Peer IP register address
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*/
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#define Sn_DIPR0(ch) (0x000C08 + (ch<<5))
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#define Sn_DIPR1(ch) (0x000D08 + (ch<<5))
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#define Sn_DIPR2(ch) (0x000E08 + (ch<<5))
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#define Sn_DIPR3(ch) (0x000F08 + (ch<<5))
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/**
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@brief Peer port register address
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*/
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#define Sn_DPORT0(ch) (0x001008 + (ch<<5))
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#define Sn_DPORT1(ch) (0x001108 + (ch<<5))
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/**
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@brief Maximum Segment Size(Sn_MSSR0) register address
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*/
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#define Sn_MSSR0(ch) (0x001208 + (ch<<5))
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#define Sn_MSSR1(ch) (0x001308 + (ch<<5))
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/**
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@brief IP Type of Service(TOS) Register
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*/
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#define Sn_TOS(ch) (0x001508 + (ch<<5))
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/**
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@brief IP Time to live(TTL) Register
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*/
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#define Sn_TTL(ch) (0x001608 + (ch<<5))
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/**
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@brief Receive memory size reigster
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*/
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#define Sn_RXMEM_SIZE(ch) (0x001E08 + (ch<<5))
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/**
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@brief Transmit memory size reigster
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*/
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#define Sn_TXMEM_SIZE(ch) (0x001F08 + (ch<<5))
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/**
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@brief Transmit free memory size register
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*/
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#define Sn_TX_FSR0(ch) (0x002008 + (ch<<5))
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#define Sn_TX_FSR1(ch) (0x002108 + (ch<<5))
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/**
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@brief Transmit memory read pointer register address
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*/
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#define Sn_TX_RD0(ch) (0x002208 + (ch<<5))
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#define Sn_TX_RD1(ch) (0x002308 + (ch<<5))
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/**
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@brief Transmit memory write pointer register address
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*/
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#define Sn_TX_WR0(ch) (0x002408 + (ch<<5))
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#define Sn_TX_WR1(ch) (0x002508 + (ch<<5))
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/**
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@brief Received data size register
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*/
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#define Sn_RX_RSR0(ch) (0x002608 + (ch<<5))
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#define Sn_RX_RSR1(ch) (0x002708 + (ch<<5))
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/**
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@brief Read point of Receive memory
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*/
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#define Sn_RX_RD0(ch) (0x002808 + (ch<<5))
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#define Sn_RX_RD1(ch) (0x002908 + (ch<<5))
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/**
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@brief Write point of Receive memory
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*/
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#define Sn_RX_WR0(ch) (0x002A08 + (ch<<5))
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#define Sn_RX_WR1(ch) (0x002B08 + (ch<<5))
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/**
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@brief socket interrupt mask register
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*/
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#define Sn_IMR(ch) (0x002C08 + (ch<<5))
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#define IMR_SENDOK 0x10
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#define IMR_TIMEOUT 0x08
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#define IMR_RECV 0x04
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#define IMR_DISCON 0x02
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#define IMR_CON 0x01
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/**
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@brief frag field value in IP header register
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*/
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#define Sn_FRAG(ch) (0x002D08 + (ch<<5))
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/**
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@brief Keep Timer register
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*/
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#define Sn_KPALVTR(ch) (0x002F08 + (ch<<5))
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/* MODE register values */
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#define MR_RST 0x80 /**< reset */
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#define MR_WOL 0x20 /**< Wake on Lan */
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#define MR_PB 0x10 /**< ping block */
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#define MR_PPPOE 0x08 /**< enable pppoe */
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#define MR_UDP_FARP 0x02 /**< enbale FORCE ARP */
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/* IR register values */
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#define IR_CONFLICT 0x80 /**< check ip confict */
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#define IR_UNREACH 0x40 /**< get the destination unreachable message in UDP sending */
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#define IR_PPPoE 0x20 /**< get the PPPoE close message */
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#define IR_MAGIC 0x10 /**< get the magic packet interrupt */
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/* Sn_MR values */
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#define Sn_MR_CLOSE 0x00 /**< unused socket */
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#define Sn_MR_TCP 0x01 /**< TCP */
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#define Sn_MR_UDP 0x02 /**< UDP */
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#define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */
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#define Sn_MR_MACRAW 0x04 /**< MAC LAYER RAW SOCK */
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#define Sn_MR_PPPOE 0x05 /**< PPPoE */
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#define Sn_MR_UCASTB 0x10 /**< Unicast Block in UDP Multicating*/
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#define Sn_MR_ND 0x20 /**< No Delayed Ack(TCP) flag */
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#define Sn_MR_MC 0x20 /**< Multicast IGMP (UDP) flag */
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#define Sn_MR_BCASTB 0x40 /**< Broadcast blcok in UDP Multicating */
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#define Sn_MR_MULTI 0x80 /**< support UDP Multicating */
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/* Sn_MR values on MACRAW MODE */
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#define Sn_MR_MIP6N 0x10 /**< IPv6 packet Block */
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#define Sn_MR_MMB 0x20 /**< IPv4 Multicasting Block */
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//#define Sn_MR_BCASTB 0x40 /**< Broadcast blcok */
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#define Sn_MR_MFEN 0x80 /**< support MAC filter enable */
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/* Sn_CR values */
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#define Sn_CR_OPEN 0x01 /**< initialize or open socket */
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#define Sn_CR_LISTEN 0x02 /**< wait connection request in tcp mode(Server mode) */
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#define Sn_CR_CONNECT 0x04 /**< send connection request in tcp mode(Client mode) */
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#define Sn_CR_DISCON 0x08 /**< send closing reqeuset in tcp mode */
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#define Sn_CR_CLOSE 0x10 /**< close socket */
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#define Sn_CR_SEND 0x20 /**< update txbuf pointer, send data */
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#define Sn_CR_SEND_MAC 0x21 /**< send data with MAC address, so without ARP process */
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#define Sn_CR_SEND_KEEP 0x22 /**< send keep alive message */
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#define Sn_CR_RECV 0x40 /**< update rxbuf pointer, recv data */
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#ifdef __DEF_IINCHIP_PPP__
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#define Sn_CR_PCON 0x23
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#define Sn_CR_PDISCON 0x24
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#define Sn_CR_PCR 0x25
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#define Sn_CR_PCN 0x26
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#define Sn_CR_PCJ 0x27
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#endif
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/* Sn_IR values */
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#ifdef __DEF_IINCHIP_PPP__
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#define Sn_IR_PRECV 0x80
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#define Sn_IR_PFAIL 0x40
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#define Sn_IR_PNEXT 0x20
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#endif
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#define Sn_IR_SEND_OK 0x10 /**< complete sending */
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#define Sn_IR_TIMEOUT 0x08 /**< assert timeout */
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#define Sn_IR_RECV 0x04 /**< receiving data */
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#define Sn_IR_DISCON 0x02 /**< closed socket */
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#define Sn_IR_CON 0x01 /**< established connection */
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/* Sn_SR values */
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#define SOCK_CLOSED 0x00 /**< closed */
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#define SOCK_INIT 0x13 /**< init state */
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#define SOCK_LISTEN 0x14 /**< listen state */
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#define SOCK_SYNSENT 0x15 /**< connection state */
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#define SOCK_SYNRECV 0x16 /**< connection state */
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#define SOCK_ESTABLISHED 0x17 /**< success to connect */
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#define SOCK_FIN_WAIT 0x18 /**< closing state */
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#define SOCK_CLOSING 0x1A /**< closing state */
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#define SOCK_TIME_WAIT 0x1B /**< closing state */
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#define SOCK_CLOSE_WAIT 0x1C /**< closing state */
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#define SOCK_LAST_ACK 0x1D /**< closing state */
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#define SOCK_UDP 0x22 /**< udp socket */
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#define SOCK_IPRAW 0x32 /**< ip raw mode socket */
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#define SOCK_MACRAW 0x42 /**< mac raw mode socket */
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#define SOCK_PPPOE 0x5F /**< pppoe socket */
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/* IP PROTOCOL */
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#define IPPROTO_IP 0 /**< Dummy for IP */
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#define IPPROTO_ICMP 1 /**< Control message protocol */
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#define IPPROTO_IGMP 2 /**< Internet group management protocol */
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#define IPPROTO_GGP 3 /**< Gateway^2 (deprecated) */
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#define IPPROTO_TCP 6 /**< TCP */
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#define IPPROTO_PUP 12 /**< PUP */
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#define IPPROTO_UDP 17 /**< UDP */
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#define IPPROTO_IDP 22 /**< XNS idp */
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#define IPPROTO_ND 77 /**< UNOFFICIAL net disk protocol */
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#define IPPROTO_RAW 255 /**< Raw IP packet */
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#define W5500_SCS GPIO_Pin_4 //<2F><><EFBFBD><EFBFBD>W5500<30><30>CS<43><53><EFBFBD><EFBFBD>
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#define W5500_SCS_PORT GPIOA
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#define W5500_RST GPIO_Pin_0 //<2F><><EFBFBD><EFBFBD>W5500<30><30>RST<53><54><EFBFBD><EFBFBD>
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#define W5500_RST_PORT GPIOB
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#define W5500_INT GPIO_Pin_1 //<2F><><EFBFBD><EFBFBD>W5500<30><30>INT<4E><54><EFBFBD><EFBFBD>
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#define W5500_INT_PORT GPIOB
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/*********************************************************
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* iinchip access function
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*********************************************************/
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//----------------------------------define----------------------------//
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//--------------------------function-------------------------------------//
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void IINCHIP_WRITE( uint32 addrbsb, uint8 data);
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uint8 IINCHIP_READ(uint32 addrbsb);
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uint16 wiz_write_buf(uint32 addrbsb,uint8* buf,uint16 len);
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uint16 wiz_read_buf(uint32 addrbsb, uint8* buf,uint16 len);
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void iinchip_init(void); // reset iinchip
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void sysinit(uint8 * tx_size, uint8 * rx_size); // setting tx/rx buf size
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uint8 getISR(uint8 s);
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void putISR(uint8 s, uint8 val);
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uint16 getIINCHIP_RxMAX(uint8 s);
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uint16 getIINCHIP_TxMAX(uint8 s);
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void setMR(uint8 val);
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void setRTR(uint16 timeout); // set retry duration for data transmission, connection, closing ...
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void setRCR(uint8 retry); // set retry count (above the value, assert timeout interrupt)
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void clearIR(uint8 mask); // clear interrupt
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uint8 getIR( void );
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void setSn_MSS(SOCKET s, uint16 Sn_MSSR); // set maximum segment size
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uint8 getSn_IR(SOCKET s); // get socket interrupt status
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uint8 getSn_SR(SOCKET s); // get socket status
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uint16 getSn_TX_FSR(SOCKET s); // get socket TX free buf size
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uint16 getSn_RX_RSR(SOCKET s); // get socket RX recv buf size
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uint8 getSn_SR(SOCKET s);
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void setSn_TTL(SOCKET s, uint8 ttl);
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void send_data_processing(SOCKET s, uint8 *wizdata, uint16 len);
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void recv_data_processing(SOCKET s, uint8 *wizdata, uint16 len);
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void setGAR(uint8 * addr); // set gateway address
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void setSUBR(uint8 * addr); // set subnet mask address
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void setSHAR(uint8 * addr); // set local MAC address
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void setSIPR(uint8 * addr); // set local IP address
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void getGAR(uint8 * addr);
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void getSUBR(uint8 * addr);
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void getSHAR(uint8 * addr);
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void getSIPR(uint8 * addr);
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void setSn_IR(uint8 s, uint8 val);
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void W5500_Run(void);
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//----------------- Typedef -----------------------------//
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typedef struct {
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int (* initialize)(void);
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unsigned char mac[6];
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unsigned char ip[4];
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unsigned char sub[4];
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unsigned char gw[4];
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}W5500_T;
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//---------------- Extern -------------------------------//
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extern W5500_T w5500;
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/**
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@brief WIZCHIP_OFFSET_INC on IINCHIP_READ/WRITE
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* case1.
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* IINCHIP_WRITE(RTR0,val);
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* IINCHIP_WRITE(RTR1,val);
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* case1.
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* IINCHIP_WRITE(RTR0,val);
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* IINCHIP_WRITE(WIZCHIP_OFFSET_INC(RTR0,1));
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*/
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//#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
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#endif
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